Epson S1C17624 Technical Manual page 74

The PCLK supply cannot be disabled if one or more peripheral modules in these list must be oper-
ated. The PCLK supply can be disabled if all the peripheral circuits in these list can be stopped.
Stop the PCLK supply to reduce current consumption if all the peripheral modules listed above are
not required.
Peripheral modules/functions that do not use PCLK
• Clock timer (CT)
• Stopwatch timer (SWT)
• Watchdog timer (WDT)
• 8-bit OSC1 timer (T8OSC1)
• LCD driver (LCD)
• R/F converter (RFC)
• 16-bit PWM timer (T16A2)
• FOUTH/FOUT1 outputs
These peripheral modules/functions can operate even if PCLK is stopped.
notes: • Do not set PCKEN[1:0] to 0x2 or 0x1 and PRUN/PSC_CTL register to 0, since doing so will
stop the operation of certain peripheral modules.
• The interrupt controller (ITC) needs PCLK only when the register is set.
CClK Control Register (ClG_CClK)
Register name address Bit
CClK Control 0x5081 D7–2 –
Register (8 bits)
D1–0 CClKGR[1:0] CCLK clock gear ratio select
(ClG_CClK)
D[7:2] Reserved
D[1:0] CClKGR[1:0]: CClK Clock Gear Ratio Select Bits
Selects the gear ratio for reducing system clock speed and sets the CCLK clock speed for operating the
S1C17 Core. To reduce current consumption, operate the S1C17 Core using the slowest possible clock
speed.
S1C17624/604/622/602/621 TeChniCal Manual
name Function
reserved
Table 7. 9.7 CCLK Gear Ratio Selection
CClKGR[1:0]
0x3
0x2
0x1
0x0
Seiko epson Corporation
7 ClOCK GeneRaTOR (ClG)
Setting init. R/W
–
CCLKGR[1:0] Gear ratio 0x0 R/W
0x3 1/8
0x2 1/4
0x1 1/2
0x0 1/1
Gear ratio
1/8
1/4
1/2
1/1
(Default: 0x0)
Remarks
– – 0 when being read.
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