Epson S1C17624 Technical Manual page 116

10 Fine MODe 8-BiT TiMeRS (T8F)
10.2 Count Clock
The count clock is generated by dividing the PCLK clock into 1/1 to 1/16K. The division ratio can be selected from
the 15 types shown below using DF[3:0]/T8F_CLKx register.
DF[3:0]
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
notes: • The clock generator (CLG) must be configured to supply PCLK to the peripheral modules be-
fore running the timer.
• Make sure the counter is halted before setting the count clock.
For detailed information on the CLG control, see the "Clock Generator (CLG)" chapter.
10.3 Count Mode
The T8F module features two count modes: repeat mode and one-shot mode. These modes are selected using
TRMD/T8F_CTLx register.
Repeat mode (TRMD = 0, default)
Setting TRMD to 0 sets T8F to repeat mode.
In this mode, once the count starts, the timer continues running until stopped by the application program. When
the counter underflows, the timer presets the reload data register value into the counter and continues the count.
Thus, the timer periodically outputs an underflow pulse. T8F should be set to this mode to generate periodic
interrupts or to generate a serial transfer clock.
One-shot mode (TRMD = 1)
Setting TRMD to 1 sets T8F to one-shot mode.
In this mode, the timer stops automatically as soon as the counter underflows. This means only one interrupt
can be generated after the timer starts. Note that the timer presets the reload data register value to the counter,
then stops after an underflow has occurred. T8F should be set to this mode to set a specific wait time.
10.4 Reload Data Register and underflow Cycle
The reload data register T8F_TRx is used to set the initial value for the down counter.
The initial counter value set in the reload data register is preset to the down counter if the timer is reset or the coun-
ter underflows. If the timer is started after resetting, it counts down from the reload value (initial value). This means
that the reload value and the input clock frequency determine the time elapsed from the point at which the timer
starts until the underflow occurs (or between underflows). The time determined is used to obtain the specified wait
time, the intervals between periodic interrupts, and the programmable serial interface transfer clock.
10-2
Table 10. 2.1 PCLK Division Ratio Selection
Division ratio
Reserved
1/16384
1/8192
1/4096
1/2048
1/1024
1/512
1/256
Seiko epson Corporation
DF[3:0] Division ratio
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
S1C17624/604/622/602/621 TeChniCal Manual
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
(Default: 0x0)