Epson S1C17624 Technical Manual page 297

Debug Control Register (DCR)
Register name address Bit
Debug Control 0xffffa0
D7
Register
(8 bits)
D6
(DCR)
D5
D4
D3
D2
D1
D0
D7 iBe4: instruction Break #4 enable Bit
Enables or disables instruction break #4.
1 (R/W): Enabled
0 (R/W): Disabled (default)
If this bit is set to 1, the instruction fetch address and the value set in the IBAR4 register are compared.
If they match, an instruction break is generated. If this bit is set to 0, no comparison is performed.
D6 iBe3: instruction Break #3 enable Bit
Enables or disables instruction break #3.
1 (R/W): Enabled
0 (R/W): Disabled (default)
If this bit is set to 1, the instruction fetch address and the value set in the IBAR3 register are compared.
If they match, an instruction break is generated. If this bit is set to 0, no comparison is performed.
D5 iBe2: instruction Break #2 enable Bit
Enables or disables instruction break #2.
1 (R/W): Enabled
0 (R/W): Disabled (default)
If this bit is set to 1, the instruction fetch address and the value set in the IBAR2 register are compared.
If they match, an instruction break is generated. If this bit is set to 0, no comparison is performed.
D4 DR: Debug Request Flag Bit
Indicates the presence or absence of an external debug request.
1 (R): Request generated
0 (R): Request not generated (default)
1 (W): Flag is reset
0 (W): Ignored
This flag is cleared (reset to 0) when 1 is written. It must be cleared before the debug processing routine
is terminated by the retd instruction.
D3 iBe1: instruction Break #1 enable Bit
Enables or disables instruction break #1.
1 (R/W): Enabled
0 (R/W): Disabled (default)
If this bit is set to 1, the instruction fetch address and the value set in the IBAR1 register are compared.
If they match, an instruction break is generated. If this bit is set to 0, no comparison is performed.
D2 iBe0: instruction Break #0 enable Bit
Enables or disables instruction break #0.
1 (R/W): Enabled
0 (R/W): Disabled (default)
If this bit is set to 1, the instruction fetch address and the value set in the IBAR0 register are compared.
If they match, an instruction break is generated. If this bit is set to 0, no comparison is performed.
S1C17624/604/622/602/621 TeChniCal Manual
name Function
iBe4
Instruction break #4 enable
iBe3
Instruction break #3 enable
iBe2 Instruction break #2 enable
DR
Debug request flag
iBe1
Instruction break #1 enable
iBe0 Instruction break #0 enable
Se
Single step enable
DM
Debug mode
Seiko epson Corporation
27 On-ChiP DeBuGGeR (DBG)
Setting init. R/W
1 Enable 0 Disable
1 Enable 0 Disable
1 Enable 0 Disable
1 Occurred 0 Not occurred
1 Enable 0 Disable
1 Enable 0 Disable
1 Enable 0 Disable
1 Debug mode 0 User mode
Remarks
0 R/W
0 R/W
0 R/W
0 R/W Reset by writing 1.
0 R/W
0 R/W
0 R/W
0 R
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