Epson S1C17624 Technical Manual page 62

Oscillation enable bit
(IOSCEN/OSC3EN/OSC1EN)
Oscillation waveform
Digitized oscillation waveform
Oscillator output clock
(f
IOSC
Figure 7.
The IOSC clock is not supplied to the system until the time set for this circuit has elapsed. Use IOSCWT[1:0]/
OSC_CTL register to select one of four oscillation stabilization wait times.
This is set to 64 cycles (IOSC clock) after an initial reset. This means the CPU can start operating when the
CPU operation start time at initial reset indicated below (at a maximum) has elapsed after the reset state is can-
celed. For the oscillation start time, see the "Electrical Characteristics" chapter.
CPU operation start time at initial reset ≤ IOSC oscillation start time (max.) + IOSC oscillation stabilization
wait time (64 cycles)
When the system clock is switched to IOSC immediately after turning the IOSC oscillator on, the IOSC clock
is supplied to the system after the IOSC clock system supply wait time indicated below (at a maximum) has
elapsed. If the power supply voltage V
the oscillation stabilization wait time.
IOSC clock system supply wait time ≤ IOSC oscillation start time (max.) + IOSC oscillation stabilization
wait time
7.3.2 OSC3 Oscillator
The OSC3 oscillator is a high-precision, high-speed oscillator circuit that uses either a crystal resonator or a ceramic
resonator. It can be switched for use with the IOSC oscillator. Figure 7.3.2.1 shows the OSC3 oscillator configuration.
C
G3
R
V C
SS D3
A crystal resonator (X'tal3) or a ceramic resonator (Ceramic) and a feedback resistor (R
between the OSC3 and OSC4 pins. Additionally, two capacitors (C
OSC3/OSC4 pins and V
SS
S1C17624/604/622/602/621 TeChniCal Manual
System supply wait time
/f /f )
OSC3 OSC1
3.1.2 Oscillation Start Time and Oscillation Stabilization Wait Time
Table 7. 3.1.1 IOSC Oscillation Stabilization Wait Time Settings
iOSCWT[1:0]
0x3
0x2
0x1
0x0
has stabilized sufficiently, IOSCWT[1:0] can be set to 0x3 to reduce
DD
OSC3
X'tal3
or
f3
Ceramic
OSC4
Figure 7. 3.2.1 OSC3 Oscillator Circuit
.
Seiko epson Corporation
Oscillation start time
Oscillation stabilization wait time
Oscillation stabilization wait time
8 cycles
16 cycles
32 cycles
64 cycles
OSC3EN
SLEEP/NORMAL
Oscillation stabilization
wait circuit
R
OSC3WT[1:0]
D3
and C
G3
7 ClOCK GeneRaTOR (ClG)
(Default: 0x0)
f
OSC3
) should be connected
f3
) should be connected between the
D3
7-3