Epson S1C17624 Technical Manual page 204

19 SPi
An interrupt occurs if other interrupt conditions are met. You can inspect the SPRBF flag in the SPI interrupt
handler routine to determine whether the SPI interrupt is attributable to a receive buffer full. If SPRBF is 1, the
received data can be read from the receive data buffer by the interrupt handler routine.
For more information on interrupt processing, see the "Interrupt Controller (ITC)" chapter.
19.7 Control Register Details
address
0x4320 SPI_ST0 SPI Ch.0 Status Register
0x4322 SPI_TXD0 SPI Ch.0 Transmit Data Register
0x4324 SPI_RXD0 SPI Ch.0 Receive Data Register
0x4326 SPI_CTL0 SPI Ch.0 Control Register
The SPI registers are described in detail below. These are 16-bit registers.
note: When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1.
SPi Ch.x Status Register (SPi_STx)
Register name address Bit
SPi Ch.x Status 0x4320 D15–3 –
Register (16 bits)
D2
(SPi_STx)
D1
D0
D[15:3] Reserved
D2 SPBSY: Transfer Busy Flag Bit (Master Mode)/ss Signal low Flag Bit (Slave Mode)
Master mode
Indicates the SPI transfer status.
1 (R): Operating
0 (R): Standby (default)
SPBSY is set to 1 when the SPI starts data transfer in master mode and is maintained at 1 while transfer
is underway. It is cleared to 0 once the transfer is complete.
Slave mode
Indicates the slave selection (#SPISSx) signal status.
1 (R): Low level (this SPI is selected)
0 (R): High level (this SPI is not selected) (default)
SPBSY is set to 1 when the master device asserts the #SPISSx signal to select this SPI module (slave
device). It is returned to 0 when the master device clears the SPI module selection by negating the
#SPISSx signal.
D1 SPRBF: Receive Data Buffer Full Flag Bit
Indicates the receive data buffer status.
1 (R): Data full
0 (R): No data (default)
SPRBF is set to 1 when data received in the shift register is sent to the receive data buffer (when receiv-
ing is completed), indicating that the data can be read. It reverts to 0 once the buffer data is read from
the SPI_RXDx register.
D0 SPTBe: Transmit Data Buffer empty Flag Bit
Indicates the transmit data buffer status.
1 (R): Empty (default)
0 (R): Data exists
19-6
Table 19. 7.1 List of SPI Registers
Register name
name Function
reserved
SPBSY Transfer busy flag (master)
ss signal low flag (slave)
SPRBF Receive data buffer full flag
SPTBe
Transmit data buffer empty flag
Seiko epson Corporation
Function
Indicates transfer and buffer statuses.
Transmit data
Receive data
Sets the SPI mode and enables data transfer.
Setting
–
1 Busy 0 Idle
1 ss = L 0 ss = H
1 Full 0 Not full
1 Empty 0 Not empty
S1C17624/604/622/602/621 TeChniCal Manual
init. R/W Remarks
– – 0 when being read.
0 R
0 R
1 R