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Table 7.4.2 lists the combinations of clock operating states and register settings enabling sys-
tem clock (OSC1 or HSCLK) selection.
iOSC
On
On
Off
• When switching the HSCLK source (IOSC↔OSC3), always make sure that PCKEN[1:0]/CLG_
PCLK register is set to 0x3 before writing to HSCLKSEL.
• The oscillator circuit selected as the system clock source cannot be turned off.
• Continuous write/read access to CLKSRC is prohibited. At least one instruction unrelated to
CLKSRC access must be inserted between the write and read instructions.
• Canceling HALT/SLEEP mode does not change the clock status configured before the chip
entered HALT/SLEEP mode.
7.5
CPu Core Clock (CClK) Control
The CLG module includes a clock gear to slow down the system clock to send to the S1C17 Core. To reduce cur-
rent consumption, operate the S1C17 Core with the slowest possible clock speed. The halt instruction can be ex-
ecuted to stop the clock supply from the CLG to the S1C17 Core for power savings.
HSCLK
OSC1
Clock gear settings
CCLKGR[1:0]/CLG_CCLK register is used to select the gear ratio to reduce system clock speeds.
Clock supply control
The CCLK clock supply is stopped by executing the halt instruction. Since this does not stop the system
clock, peripheral modules will continue to operate.
HALT mode is cleared by resetting, NMI, or other interrupts. The CCLK supply resumes when HALT mode is
cleared.
Executing the slp instruction suspends system clock supply to the CLG, thereby halting the CCLK supply as
well. Clearing SLEEP mode with an external interrupt restarts the system clock supply and the CCLK supply.
7.6
Peripheral Module Clock (PClK) Control
The CLG module also controls the clock supply to peripheral modules.
The system clock is used unmodified for the peripheral module clock (PCLK).
S1C17624/604/622/602/621 TeChniCal Manual
Table 7.
4.2 System Clock Switching (OSC1
OSC3
OSC1
On
On
Off
On
On
On
Gear selection
System clock
Clock gear
(1/1–1/8)
Figure 7.
5.1 CCLK Supply System
Table 7.
5.1 CCLK Gear Ratio Selection
CClKGR[1:0]
0x3
0x2
0x1
0x0
Seiko epson Corporation
7 ClOCK GeneRaTOR (ClG)
↔HSCLK) Conditions
hSClKSel
System clock
*
IOSC/OSC3 or OSC1
0
IOSC or OSC1
1
OSC3 or OSC1
HALT
Gate
CCLK
Gear ratio
1/8
1/4
1/2
1/1
(Default: 0x0)
S1C17 Core
7-7
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