Epson S1C17624 Technical Manual page 59

• When data is written to the ITC_LV0 to ITC_LV9 registers, the "Reserved" bits must always be
written as 0 and not 1.
interrupt level Setup Register x (iTC_lVx)
Register name address Bit
interrupt level 0x4306 D15–11 –
Setup Register x |
D10–8 ilVn[2:0]
(iTC_lVx) 0x4318
D7–3 –
(16 bits)
D2–0 ilVn[2:0]
D[15:11], D[7:3]
Reserved
D[10:8], D[2:0]
ilVn[2:0]: INTn interrupt level Bits (n = 0–19)
Sets the interrupt level (0 to 7) of each interrupt. (Default: 0x0)
The S1C17 Core does not accept interrupts with a level set lower than the PSR IL value.
The ITC uses the interrupt level when multiple interrupt requests occur simultaneously.
If multiple interrupt requests enabled by the interrupt enable bit occur simultaneously, the ITC sends the
interrupt request with the highest level set by the ITC_LVx registers (0x4306 to 0x4318) to the S1C17
Core.
If multiple interrupt requests with the same interrupt level occur simultaneously, the interrupt with the
lowest vector number is processed first.
The other interrupts are held until all interrupts of higher priority have been accepted by the S1C17
Core.
If an interrupt requests of higher priority occurs while the ITC outputs an interrupt request signal to the
S1C17 Core (before acceptance by the S1C17 Core), the ITC alters the vector number and interrupt
level signals to the setting details of the most recent interrupt. The immediately preceding interrupt is
held.
Register
ITC_LV0(0x4306)
ITC_LV1(0x4308)
ITC_LV2(0x430a)
ITC_LV3(0x430c)
ITC_LV4(0x430e)
ITC_LV5(0x4310)
ITC_LV6(0x4312)
ITC_LV7(0x4314)
ITC_LV8(0x4316)
ITC_LV9(0x4318)
S1C17624/604/622/602/621 TeChniCal Manual
name Function
reserved
INTn (1, 3, ... 19) interrupt level
reserved
INTn (0, 2, ... 18) interrupt level
Table 6. 7.2 Interrupt Level Bits
Bit
ILV0[2:0] (D[2:0]) P0 port interrupt
ILV1[2:0] (D[10:8]) P1 port interrupt
ILV2[2:0] (D[2:0]) Stopwatch timer (SWT) interrupt
ILV3[2:0] (D[10:8]) Clock timer (CT) interrupt / Real-time clock (RTC) interrupt
(S1C17624/604)
ILV4[2:0] (D[2:0]) 8-bit OSC1 timer (T8OSC1) interrupt
ILV5[2:0] (D[10:8]) Supply voltage detector (SVD) interrupt
ILV6[2:0] (D[2:0]) LCD driver (LCD) interrupt / 16-bit PWM timer (T16A2) Ch.0
interrupt (S1C17624/604)
ILV7[2:0] (D[10:8]) 16-bit PWM timer (T16E) Ch.0 interrupt
ILV8[2:0] (D[2:0]) 8-bit timer (T8F) Ch.0 & Ch.1 interrupt
ILV9[2:0] (D[10:8]) 16-bit timer (T16) Ch.0 interrupt
ILV10[2:0] (D[2:0]) 16-bit timer (T16) Ch.1 interrupt
ILV11[2:0] (D[10:8]) 16-bit timer (T16) Ch.2 interrupt
ILV12[2:0] (D[2:0]) UART Ch.0 interrupt
2
ILV13[2:0] (D[10:8]) I C slave (I2CS) interrupt / UART Ch.1 interrupt
ILV14[2:0] (D[2:0]) SPI Ch.0 interrupt
2
ILV15[2:0] (D[10:8]) I C master (I2CM) interrupt
ILV16[2:0] (D[2:0]) IR remote controller (REMC) interrupt
ILV17[2:0] (D[10:8]) 16-bit PWM timer (T16A2) Ch.1 interrupt (S1C17624/604)
ILV18[2:0] (D[2:0]) A/D converter (ADC10) interrupt
ILV19[2:0] (D[10:8]) R/F converter (RFC) interrupt
Seiko epson Corporation
6 inTeRRuPT COnTROlleR (iTC)
Setting init. R/W
– – – 0 when being read.
0 to 7 0x0 R/W
– – – 0 when being read.
0 to 7 0x0 R/W
interrupt
Remarks
6-7