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D6
FeR: Framing error Flag Bit
Indicates whether a framing error has occurred or not.
1 (R):
Error occurred
0 (R):
No error (default)
1 (W):
Reset to 0
0 (W):
Ignored
FER is set to 1 when a framing error occurs. Framing errors occur when data is received with the stop
bit set to 0. FER is reset by writing 1.
D5
PeR: Parity error Flag Bit
Indicates whether a parity error has occurred or not.
1 (R):
Error occurred
0 (R):
No error (default)
1 (W):
Reset to 0
0 (W):
Ignored
PER is set to 1 when a parity error occurs. Parity checking is enabled only when PREN/ UART_MODx
register is set to 1 and is performed when received data is transferred from the shift register to the re-
ceive data buffer. PER is reset by writing 1.
D4
OeR: Overrun error Flag Bit
Indicates whether an overrun error has occurred or not.
1 (R):
Error occurred
0 (R):
No error (default)
1 (W):
Reset to 0
0 (W):
Ignored
OER is set to 1 when an overrun error occurs. Overrun errors occur if the receive data buffer is full
when data is received in the shift register. The receive data buffer is not overwritten even if this error
occurs. The shift register is overwritten as soon as the error occurs.
OER is reset by writing 1.
D3
RD2B: Second Byte Receive Flag Bit
Indicates that the receive data buffer contains two received data.
1 (R):
Second byte can be read
0 (R):
Second byte not received (default)
RD2B is set to 1 when the second byte of data is loaded into the receive data buffer and is reset to 0
when the first data is read from the receive data buffer.
D2
TRBS: Transmit Busy Flag Bit
Indicates the transmit shift register status.
1 (R):
Operating
0 (R):
Standby (default)
TRBS is set to 1 when transmit data is loaded from the transmit data buffer into the shift register and is
reset to 0 when the data transfer is completed. Inspect TRBS to determine whether the transmit circuit
is operating or at standby.
D1
RDRY: Receive Data Ready Flag Bit
Indicates that the receive data buffer contains valid received data.
1 (R):
Data can be read
0 (R):
Buffer empty (default)
RDRY is set to 1 when received data is loaded into the receive data buffer and is reset to 0 when all data
has been read from the receive data buffer.
S1C17624/604/622/602/621 TeChniCal Manual
Seiko epson Corporation
18 uaRT
18-9
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