Epson S1C17624 Technical Manual page 283

The R/F converter registers are described in detail below.
note: When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1.
RFC Clock Control Registers (OSC_RFC)
Register name address Bit
RFC Clock 0x5067 D7–4 –
D3–2 RFTCKDV
Control Register (8 bits)
(OSC_RFC)
D1
D0
D[7:4] Reserved
D[3:2] RFTCKDV[1:0]: RFC Clock Division Ratio Select Bits
Selects the division ratio for generating the TCCLK clock when HSCLK (IOSC or OSC3) is used as the
clock source.
D1 RFTCKSRC: RFC Clock Source Select Bit
Selects the count clock source.
1 (R/W): OSC1 (default)
0 (R/W): HSCLK (IOSC or OSC3)
D0 RFTCKen: RFC Clock enable Bit
Enables or disables the TCCLK clock supply.
1 (R/W): Enabled (on)
0 (R/W): Disabled (off) (default)
The RFTCKEN default setting is 0, which disables the clock supply. Setting RFTCKEN to 1 sends the
clock selected to the R/F converter.
RFC Control Register (RFC_CTl)
Register name address Bit
RFC Control 0x53a0 D15–8 –
Register (16 bits)
D7
(RFC_CTl)
D6
D5–4 SMODe[1:0] Sensor oscillation mode select
D3–2 –
D1
D0
D[15:8] Reserved
D7 COnen: Continuous Oscillation enable Bit
Enables continuous oscillation by disabling the automatic CR oscillation stop function.
1 (R/W): Continuous oscillation enabled
0 (R/W): Continuous oscillation disabled (default)
S1C17624/604/622/602/621 TeChniCal Manual
name Function
reserved
RFC clock division ratio select
[1:0]
RFTCKSRC RFC clock source select
RFTCKen
RFC clock enable
Table 25. 8.2 HSCLK Division Ratio Selection
RFTCKDV[1:0]
0x3
0x2
0x1
0x0
name Function
reserved
COnen Continuous oscillation enable
eVTen
Event counter mode enable
reserved
ChSel
Conversion channel select
RFCen RFC enable
Seiko epson Corporation
25 R/F COnVeRTeR (RFC)
Setting init. R/W
–
RFTCKDV[1:0] Division ratio 0x0 R/W When the clock
1/8
0x3
0x2 1/4
0x1 1/2
1/1
0x0
1 OSC1 0 HSCLK
1 Enable 0 Disable
Division ratio
1/8
1/4
1/2
1/1
(Default: 0x0)
Setting init. R/W
–
1 Enable 0 Disable
1 Enable 0 Disable
SMODE[1:0] Sensor 0x0 R/W
0x3 reserved
0x2 DC capacitive
0x1 AC resistive
0x0 DC resistive
–
1 Ch.1 0 Ch.0
1 Enable 0 Disable
Remarks
– – 0 when being read.
source is HSCLK
1 R/W
0 R/W
Remarks
– – 0 when being read.
0 R/W
0 R/W
– – 0 when being read.
0 R/W
0 R/W
25-9