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0
BCD100[0]
1/100-second
BCD100[1]
counter
BCD100[2]
BCD data
BCD100[3]
100 Hz interrupt
10 Hz interrupt
BCD10[0]
1/10-second
BCD10[1]
counter
BCD10[2]
BCD data
BCD10[3]
1 Hz interrupt
notes: • The timer switches to Run/Stop status synchronized with the 256 Hz signal falling edge after
data is written to SWTRUN. When 0 is written to SWTRUN, the timer stops after counting an
additional "+1." 1 is retained for SWTRUN reading until the timer actually stops.
Figure 16.5.2 shows the Run/Stop control timing chart.
SWT_BCNT register
• Executing the slp instruction while the timer is running (SWTRUN = 1) will destabilize the
timer operation during restarting from SLEEP status. When switching to SLEEP status, stop
the timer (SWTRUN = 0) before executing the slp instruction.
16.6
SWT interrupts
The SWT module includes functions for generating the following three kinds of interrupts:
100 Hz, 10 Hz, and 1 Hz interrupts
The SWT module outputs a single interrupt signal shared by the above three interrupt causes to the interrupt control-
ler (ITC). The interrupt flag in the SWT module should be read to identify the cause of interrupt that occurred.
100 hz, 10 hz, 1 hz interrupts
The 100 Hz (approximate 100 Hz), 10 Hz (approximate 10 Hz), and 1 Hz signal falling edges set the corre-
sponding interrupt flag in the SWT module to 1. At the same time, an interrupt request is sent to the ITC if the
corresponding interrupt enable bit has been set to 1 (interrupt enabled). An interrupt is generated if the ITC and
S1C17 Core interrupt conditions are satisfied.
If the interrupt enable bit is set to 0 (interrupt disabled, default), no interrupt request will be sent to the ITC.
Cause of interrupt
100 Hz Interrupt
10 Hz Interrupt
1 Hz Interrupt
For specific information on interrupt processing, see the "Interrupt Controller (ITC)" chapter.
S1C17624/604/622/602/621 TeChniCal Manual
1
2
3
4
5
6
7
Figure 16.
5.1 SWT Timing Chart
256 Hz
SWTRUN(RD)
SWTRUN(WR)
27
Figure 16.
5.2 Run/Stop Control Timing Chart
Table 16.
6.1 SWT Interrupt Flags and Interrupt Enable Bits
interrupt flag
SIF100/SWT_IFLG register
SIF10/SWT_IFLG register
SIF1/SWT_IFLG register
Seiko epson Corporation
8
9
0
1
2
3
4
28
29
30
31
interrupt enable bit
SIE100/SWT_IMSK register
SIE10/SWT_IMSK register
SIE1/SWT_IMSK register
16 STOPWaTCh TiMeR (SWT)
5
6
7
8
9
0
1
32
2
3
4
16-3
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