Epson S1C17624 Technical Manual page 203

PCLK
SPEN
Write
SPI_TXDx register
Shift register
SPICLKx pin
(CPOL = 0, CPHA = 1)
SPICLKx pin
(CPOL = 0, CPHA = 0)
SDOx pin
SDIx pin
SPI_RXDx register
SPBSY
SPTBE
SPRBF
Figure 19.
Disabling data transfers
After a data transfer is completed (both transmission and reception), write 0 to SPEN to disable data transfers.
Confirm that the SPTBE flag is 1 and the SPBSY flag is 0 before disabling data transfer.
The data being transferred cannot be guaranteed if SPEN is set to 0 while data is being sent or received.
19.6 SPi interrupts
Each channel of the SPI module includes a function for generating the following two different types of interrupts.
• Transmit buffer empty interrupt
• Receive buffer full interrupt
The SPI channel outputs one interrupt signal shared by the two above interrupt causes to the interrupt controller (ITC).
Inspect the status flag to determine the interrupt cause occurred.
Transmit buffer empty interrupt
To use this interrupt, set SPTIE/SPI_CTLx register to 1. If SPTIE is set to 0 (default), interrupt requests for this
cause will not be sent to the ITC.
When transmit data written to the transmit data buffer is transferred to the shift register, the SPI module sets
SPTBE/SPI_STx register to 1, indicating that the transmit data buffer is empty. If transmit buffer empty inter-
rupts are enabled (SPTIE = 1), an interrupt request is sent simultaneously to the ITC.
An interrupt occurs if other interrupt conditions are met. You can inspect the SPTBE flag in the SPI interrupt
handler routine to determine whether the SPI interrupt is attributable to a transmit buffer empty. If SPTBE is 0,
the next transmit data can be written to the transmit data buffer by the interrupt handler routine.
note: In the S1C17602/621, the transmit buffer empty interrupt can only be used in master mode. In
the S1C17624/604/622, the transmit buffer empty interrupt can be used in both master and slave
modes.
Receive buffer full interrupt
To use this interrupt, set SPRIE/SPI_CTLx register to 1. If SPRIE is set to 0 (default), interrupt requests for this
cause will not be sent to the ITC.
When data received in the shift register is loaded into the receive data buffer, the SPI module sets SPRBF/SPI_
STx register to 1, indicating that the receive data buffer contains readable received data. If receive buffer full
interrupts are enabled (SPRIE = 1), an interrupt request is output to the ITC at the same time.
S1C17624/604/622/602/621 TeChniCal Manual
Write
Data A Data B
A A A A A A
D7 D6 D5 D4 D3
A' A' A' A' A' A'
D7 D6 D5 D4 D3
5.2 Data Transmission/Receiving Timing Chart (MSB first)
Seiko epson Corporation
Write
A A B B B
D2 D1 D0 D7 D6 D5
A' A' B' B' B'
D2 D1 D0 D7 D6 D5
Read
Data C
B B B B B
D4 D3 D2 D1 D0
B' B' B' B' B'
D4 D3 D2 D1 D0
Data A'
19 SPi
Data B'
Read
19-5