Epson S1C17624 Technical Manual page 125

11 16-BiT TiMeRS (T16)
11.2 T16 input Pins
Table 11.2.1 lists the input pins for the T16 module.
Pin name
EXCL0
EXCL1
EXCL2
The T16 input pins (EXCLx) are shared with I/O ports. Setting the port to input mode enables it to be used as the
T16 input pin with a general-purpose input function. For detailed information on the port control, see the "I/O Ports
(P)" chapter.
11.3 Operating Modes
The T16 module has the following three operating modes:
1. Internal clock mode (normal timer for counting an internal clock)
2. External clock mode (functions as an event counter)
3. Pulse width measurement mode (measures the external input pulse width using an internal clock)
The operating mode is selected using CKSL[1:0]/T16_CTLx register.
11.3.1 internal Clock Mode
Internal clock mode uses a divided PCLK clock as the count clock.
The timer counts down from the initial value set in the reload data register and outputs an underflow signal when
the counter underflows. The underflow signal is used to generate an interrupt and an internal serial interface clock.
The time until underflow occurs can be finely programmed by selecting the clock division ratio and initial counter
value, making it useful for serial transfer clock generation and sporadic time measurement.
Count clock selection
The count clock is generated by dividing the PCLK clock into 1/1 to 1/16K. The division ratio can be selected
from the 15 types shown below using DF[3:0]/T16_CLKx register.
DF[3:0]
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
11-2
Table 11. 2.1 List of T16 Pins
i/O Qty
I 1 Ch.0 external clock input pin
Inputs an external clock for the event counter function or an external sig-
nal for measuring the pulse width.
I 1 Ch.1 external clock input pin
Inputs an external clock for the event counter function or an external sig-
nal for measuring the pulse width.
I 1 Ch.2 external clock input pin
Inputs an external clock for the event counter function or an external sig-
nal for measuring the pulse width.
Table 11. 3.1 Operating Mode Selection
CKSl[1:0]
0x3
0x2
0x1
0x0
Table 11. 3.1.1 PCLK Division Ratio Selection
Division ratio
Reserved
1/16384
1/8192
1/4096
1/2048
1/1024
1/512
1/256
Seiko epson Corporation
Function
Operating mode
Reserved
Pulse width measurement mode
External clock mode
Internal clock mode
(Default: 0x0)
DF[3:0]
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
S1C17624/604/622/602/621 TeChniCal Manual
Division ratio
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
(Default: 0x0)