Epson S1C17624 Technical Manual page 92

9 i/O PORTS (P)
• The I/O ports shown below allow software to select the input interface level from two types:
CMOS Schmitt level and CMOS level.
S1C17624/622: P0[7:0], P1[5:0], P4[7:4], P5[2:0]
S1C17604/602/621: P0[7:0], P1[5:0]
The I/O ports shown below support only CMOS Schmitt level. (* P43 is an output-only port.)
S1C17624/622: P1[7:6], P2[7:0], P3[7:0], P40, DSIO/P41, DST2/P42, DCLK/P43*, P5[6:3]
S1C17604/602/621: P1[7:6], P2[7:0], P3[7:0], P40, DSIO/P41, DST2/P42, DCLK/P43*
9.2 input/Output Pin Function Selection (Port MuX)
The I/O port pins share peripheral module input/output pins. Each pin can be configured for use as an I/O port or
for a peripheral module function via the corresponding port function-select bits. Pins not used for peripheral mod-
ules can be used as general-purpose I/O ports.
Pin function 1 Pin function 2
PxyMuX[1:0] = 0x0 PxyMuX[1:0] = 0x1
P00 REMO (REMC)
P01
REMI (REMC)
P02/eXCl0 (T16) *1
P03
#ADTRG (ADC10)
P04
SPICLK0 (SPI)
P05 SDO0 (SPI)
P06 SDI0 (SPI)
P07
#SPISS0 (SPI)
P10
SCLK0 (UART)
P11
SOUT0 (UART)
P12
SIN0 (UART)
P13/eXCl1 (T16) *1
P14/eXCl2 (T16) *1
P15/eXCl3 (T16E) *1
P16
SCLK1 (UART)
P17
AIN3 (ADC10)
P20
AIN2 (ADC10)
P21 AIN1 (ADC10)
P22
AIN0 (ADC10)
P23
SENB0 (RFC)
P24
SENA0 (RFC)
P25
REF0 (RFC)
P26 RFIN0 (RFC)
P27 SOUT1 (UART)
P30
SIN1 (UART)
P31
SCL0 (I2CM)
P32
SDA0 (I2CM)
P33
SCL1 (I2CS)
P34 SDA1 (I2CS)
P35 FOUT1 (CLG)
P36/eXCl5 (T16A2) *1
TOUT3 (T16E)
P37/eXCl6 (T16A2) *1
TOUTN3 (T16E)
P40
FOUTH (CLG)
DSiO (DBG)
P41
DST2 (DBG) P42
DClK (DBG) P43 *5
P44
SCL1 (I2CS)
P45
SDA1 (I2CS)
P46
RFCLKO (RFC)
P47/eXCl5 (T16A2) *2 TOUT4 (T8OSC1)
P50/eXCl6 (T16A2) *2 SCLK1 (UART)
P51
SOUT1 (UART)
P52
SIN1 (UART)
P53
#BFR (I2CS)
P54
LFRO (LCD)
P55
P56
*1: The P02, P13–P15, P36, P37, P47, and P50 pins can also be used as an external clock input pin for the timer module by setting
them to input mode. However, general-purpose input port function is also effective in this case. In the S1C17624, either P36 or
P47 can be selected as the EXCL5 input port and either P37 or P50 can be selected as the EXCL6 input port using EXCL5S/
P54_56PMUX register and EXCL6S/P54_56PMUX register. P36 and P37 are only available in the S1C17604.
9-2
Table 9. 2.1 Input/Output Pin Function Selection
Pin function 3
PxyMuX[1:0] = 0x2
–
–
– –
–
–
–
–
–
–
–
–
– AIN7 (ADC10)
– AIN6 (ADC10)
– AIN5 (ADC10)
AIN4 (ADC10)
–
–
–
–
–
–
–
–
RFIN1 (RFC)
REF1 (RFC)
SENA1 (RFC)
SENB1 (RFC)
SCL0 (I2CM)
SDA0 (I2CM)
#BFR (I2CS)
RFCLKO (RFC)
LFRO (LCD)
–
–
–
–
–
–
–
–
–
TOUTA5/CAPA5 (T16A2)
TOUTB5/CAPB5 (T16A2)
–
–
– TOUTA6/CAPA6 (T16A2)
– TOUTB6/CAPB6 (T16A2)
Seiko epson Corporation
Pin function 4
PxyMuX[1:0] = 0x3
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*3
TOUTA5/CAPA5 (T16A2)
TOUTB5/CAPB5 (T16A2) *3
TOUTA6/CAPA6 (T16A2) *3
TOUTB6/CAPB6 (T16A2) *3
–
–
TOUT4 (T8OSC1)
–
–
–
–
–
–
–
–
–
*2
–
*2
–
–
–
*2 –
*2 –
S1C17624/604/622/602/621 TeChniCal Manual
Port function select bits
(bit/register)
P00MUX[1:0]/P00_03PMUX
P01MUX[1:0]/P00_03PMUX
P02MUX[1:0]/P00_03PMUX
P03MUX[1:0]/P00_03PMUX
P04MUX[1:0]/P04_07PMUX
P05MUX[1:0]/P04_07PMUX
P06MUX[1:0]/P04_07PMUX
P07MUX[1:0]/P04_07PMUX
P10MUX[1:0]/P10_13PMUX
P11MUX[1:0]/P10_13PMUX
P12MUX[1:0]/P10_13PMUX
P13MUX[1:0]/P10_13PMUX
P14MUX[1:0]/P14_17PMUX
P15MUX[1:0]/P14_17PMUX
P16MUX[1:0]/P14_17PMUX
P17MUX[1:0]/P14_17PMUX
P20MUX[1:0]/P20_23PMUX
P21MUX[1:0]/P20_23PMUX
P22MUX[1:0]/P20_23PMUX
P23MUX[1:0]/P20_23PMUX
P24MUX[1:0]/P24_27PMUX
P25MUX[1:0]/P24_27PMUX
P26MUX[1:0]/P24_27PMUX
P27MUX[1:0]/P24_27PMUX
P30MUX[1:0]/P30_33PMUX
P31MUX[1:0]/P30_33PMUX
P32MUX[1:0]/P30_33PMUX
P33MUX[1:0]/P30_33PMUX
P34MUX[1:0]/P34_37PMUX
P35MUX[1:0]/P34_37PMUX
P36MUX[1:0]/P34_37PMUX
P37MUX[1:0]/P34_37PMUX
P40MUX[1:0]/P40_43PMUX
P41MUX[1:0]/P40_43PMUX
P42MUX[1:0]/P40_43PMUX
P43MUX[1:0]/P40_43PMUX
*4
P44MUX[1:0]/P44_47PMUX
P45MUX[1:0]/P44_47PMUX *4
P46MUX[1:0]/P44_47PMUX *4
P47MUX[1:0]/P44_47PMUX *4
P50MUX[1:0]/P50_53PMUX *4
*4
P51MUX[1:0]/P50_53PMUX
*4
P52MUX[1:0]/P50_53PMUX
P53MUX[1:0]/P50_53PMUX *4
P54MUX[1:0]/P54_56PMUX *4
P55MUX[1:0]/P54_56PMUX *4
P56MUX[1:0]/P54_56PMUX *4