Epson S1C17624 Technical Manual page 260

lCD Clock Control Register (lCD_CCTl)
Register name address Bit
lCD Clock 0x50a2 D7–6 FRMCnT[1:0] Frame frequency control
Control Register
(8 bits)
(lCD_CCTl)
D5
D4–3 –
D2–0 lDuTY[2:0] LCD duty select
D[7:6] FRMCnT[1:0]: Frame Frequency Control Bits
Sets the Frame frequency.
When the clock source is OSC1
Table 23.
Drive duty
(lDuTY[2:0] setting)
1/8 duty (0x4)
1/4 duty (0x3)
1/3 duty (0x2)
1/2 duty (0x1)
Static (0x0)
When the clock source is HSCLK
Drive duty
(lDuTY[2:0] setting)
1/8 duty (0x4)
1/4 duty (0x3)
1/3 duty (0x2)
1/2 duty (0x1)
Static (0x0)
f
HSCLK
D5 lFROuT: lFRO Output Control Bit
Controls the frame signal (LFRO) output.
1 (R/W): Output enabled (On)
0 (R/W): Output disabled (Off) (default)
Setting LFROUT 1 outputs the frame signal generated by the LCD module from the LFRO pin. Setting
it to 0 stops output and the LFRO pin goes a low level.
D[4:3] Reserved
D[2:0] lDuTY[2:0]: lCD Duty Select Bits
Selects the drive duty.
S1C17624/604/622/602/621 TeChniCal Manual
name Function
lFROuT
LFRO output control
reserved
8.5 Frame Frequency Settings (when OSC1 = 32.768 kHz)
0x0
128 Hz (1/256)
128 Hz (1/256)
130.04 Hz (1/252)
128 Hz (1/256)
128 Hz (1/256)
Table 23. 8.6 Frame Frequency Settings
0x0
× LCKDV
f
HSCLK
––––––––––––––
256
× LCKDV
f
HSCLK
––––––––––––––
256
× LCKDV
f
HSCLK
––––––––––––––
252
× LCKDV
f
HSCLK
––––––––––––––
256
× LCKDV
f
HSCLK
––––––––––––––
256
: HSCLK (IOSC or OSC3) clock frequency, LCKDV: HSCLK division ratio (1/32 to 1/512)
Seiko epson Corporation
Setting
FRMCNT[1:0] Division ratio
0x3
0x2
0x1
0x0
1 On 0 Off
–
LDUTY[2:0]
0x7–0x5 reserved
0x4
0x3
0x2
0x1
0x0
FRMCnT[1:0] setting (lClK division ratio)
0x1
64 Hz (1/512) * 48.19 Hz (1/680)
64 Hz (1/512) 48.19 Hz (1/680)
65.02 Hz (1/504) 48.12 Hz (1/681)
64 Hz (1/512) 48.19 Hz (1/680)
64 Hz (1/512) 48.19 Hz (1/680)
FRMCnT[1:0] setting
0x1
× LCKDV *
f f
HSCLK HSCLK
–––––––––––––– ––––––––––––––
512
× LCKDV
f f
HSCLK HSCLK
–––––––––––––– ––––––––––––––
512
× LCKDV
f f
HSCLK HSCLK
–––––––––––––– ––––––––––––––
504
× LCKDV
f f
HSCLK HSCLK
–––––––––––––– ––––––––––––––
512
× LCKDV
f f
HSCLK HSCLK
–––––––––––––– ––––––––––––––
512
23 lCD DRiVeR (lCD)
init. R/W Remarks
0x1 R/W Source clock: LCLK
1/1024
1/680
1/512
1/256
0 R/W
– – 0 when being read.
Duty 0x4 R/W
1/8
1/4
1/3
1/2
Static
0x2 0x3
32 Hz (1/1024)
32 Hz (1/1024)
32.5 Hz (1/1008)
32 Hz (1/1024)
32 Hz (1/1024)
* Default setting
0x2 0x3
× LCKDV × LCKDV
f
HSCLK
––––––––––––––
680 1024
× LCKDV × LCKDV
f
HSCLK
––––––––––––––
680 1024
× LCKDV × LCKDV
f
HSCLK
––––––––––––––
681 1008
× LCKDV × LCKDV
f
HSCLK
––––––––––––––
680 1024
× LCKDV × LCKDV
f
HSCLK
––––––––––––––
680 1024
* Default setting
23-17