Epson S1C17624 Technical Manual page 352

Appendix B Power Saving
Current consumption will vary dramatically, depending on CPU operating mode, operation clock frequency, and the
peripheral circuits being operated. Listed below are the control methods for saving power.
B.1 Clock Control Power Saving
This section describes clock systems that can be controlled via software and power-saving control details. For more
information on control registers and control methods, refer to the respective module sections.
System SleeP
• Execute the slp instruction
To stop the entire system, execute the slp instruction after setting RTCCE/RTC_CC register to 0. This stops
all the oscillator and peripheral circuits. Starting up the CPU from SLEEP mode is therefore limited to start-
up using a port.
If the slp instruction is executed when RTCCE = 1 and RTCSTP/RTC_CNTL0 register = 0, the OSC1 os-
cillator circuit does not stop and the RTC can be operated. In this case, the CPU can reawaken from SLEEP
mode by an RTC interrupt as well as a port interrupt.
System clocks
• Select a low-speed clock source (CLG module)
Select a low-speed oscillator for the system clock source. You can reduce current consumption by selecting
the OSC1 clock when low-speed processing is possible.
• Disable unnecessary oscillator circuits (CLG module)
Operate the oscillator comprising the system clock source. Where possible, stop the other oscillators. You can
reduce current consumption by using OSC1 as the system clock and disable the IOSC and OSC3 oscillators.
CPu clock (CClK)
• Execute the halt instruction
Execute the halt instruction when program execution by the CPU is not required—for example, when only
the display is required or for interrupt standby. The CPU enters HALT mode and suspends operations, but the
peripheral circuits maintain the status in place at the time of the halt instruction, enabling use of peripheral
circuits for timers and interrupts. You can reduce power consumption even further by suspending unneces-
sary oscillator and peripheral circuits before executing the halt instruction. The CPU is started from HALT
mode by an interrupt from a port or the peripheral circuit operating in HALT mode.
• Select a low-speed clock gear (CLG module)
The CLG module can reduce CPU clock speeds to between 1/1 and 1/8 of the system clock via the clock gear
settings. You can reduce current consumption by operating the CPU at the minimum speed required for the
application.
Peripheral clock (PClK)
• Stop PCLK (CLG module)
Stop the PCLK clock supplied from the CLG to peripheral circuits if none of the following peripheral circuits
is required.
Peripheral circuits that use PCLK
• 16-bit timer (T16)
• 8-bit timer (T8F)
• UART
• SPI
2
• I C master (I2CM)
• I 2 C slave (I2CS)
• 16-bit PWM timer (T16E)
• I/O port (P)
• MISC register (MISC)
• Power generator (VD1)
S1C17624/604/622/602/621 TeChniCal Manual
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