Epson S1C17624 Technical Manual page 351

Register name address Bit
T16a 0x542a D15–6 –
Comparator/
(16 bits)
D5
Capture Ch.1
D4
interrupt enable
D3
Register
D2
(T16a_ien1)
D1
D0
T16a 0x542c D15–6 –
Comparator/
(16 bits)
D5
Capture Ch.1
D4
interrupt Flag
D3
Register
D2
(T16a_iFlG1)
D1
D0
0xffff84–0xffffd0
Register name address Bit
Processor iD 0xffff84 D7–0 iDiR[7:0]
Register
(8 bits)
(iDiR)
Debug RaM 0xffff90 D31–24 –
Base Register (32 bits)
D23–0 DBRaM[23:0] Debug RAM base address
(DBRaM)
(S1C17624/604/
602)
Debug Control 0xffffa0
D7
Register
(8 bits)
D6
(DCR)
D5
D4
D3
D2
D1
D0
instruction 0xffffb4 D31–24 –
Break address
(32 bits) D23–0 iBaR1[23:0] Instruction break address #1
Register 1
(iBaR1)
instruction 0xffffb8 D31–24 –
Break address
(32 bits) D23–0 iBaR2[23:0] Instruction break address #2
Register 2
(iBaR2)
instruction 0xffffbc D31–24 –
Break address
(32 bits) D23–0 iBaR3[23:0] Instruction break address #3
Register 3
(iBaR3)
instruction 0xffffd0 D31–24 –
Break address (32 bits)
D23–0 iBaR4[23:0] Instruction break address #4
Register 4
(iBaR4)
S1C17624/604/622/602/621 TeChniCal Manual
name Function
reserved
CaPBOWie Capture B overwrite interrupt enable 1 Enable
CaPaOWie Capture A overwrite interrupt enable 1 Enable
CaPBie
Capture B interrupt enable
CaPaie
Capture A interrupt enable
CBie
Compare B interrupt enable
Caie Compare A interrupt enable
reserved
CaPBOWiF Capture B overwrite interrupt flag
CaPaOWiF Capture A overwrite interrupt flag
CaPBiF
Capture B interrupt flag
CaPaiF Capture A interrupt flag
CBiF
Compare B interrupt flag
CaiF Compare A interrupt flag
name Function
Processor ID
0x10: S1C17 Core
Unused (fixed at 0)
iBe4
Instruction break #4 enable
iBe3
Instruction break #3 enable
iBe2 Instruction break #2 enable
DR
Debug request flag
iBe1
Instruction break #1 enable
iBe0 Instruction break #0 enable
Se
Single step enable
DM
Debug mode
reserved
IBAR123 = MSB
IBAR10 = LSB
reserved
IBAR223 = MSB
IBAR20 = LSB
reserved
IBAR323 = MSB
IBAR30 = LSB
reserved
IBAR423 = MSB
IBAR40 = LSB
Seiko epson Corporation
aPPenDiX a liST OF i/O ReGiSTeRS
Setting init. R/W
–
0 Disable
0 Disable
1 Enable 0 Disable
1 Enable 0 Disable
1 Enable 0 Disable
1 Enable 0 Disable
–
1 Cause of 0 Cause of
interrupt interrupt not
occurred occurred
Setting init. R/W
0x10 0x10
0x0 0x0
←
S1C17624/604: 0x1fc0
S1C17602: 0x0fc0
1 Enable 0 Disable
1 Enable 0 Disable
1 Enable 0 Disable
1 Occurred 0 Not occurred
1 Enable 0 Disable
1 Enable 0 Disable
1 Enable 0 Disable
1 Debug mode 0 User mode
–
0x0 to 0xffffff 0x0 R/W
–
0x0 to 0xffffff 0x0 R/W
–
0x0 to 0xffffff 0x0 R/W
–
0x0 to 0xffffff 0x0 R/W
Remarks
– – 0 when being read.
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
– – 0 when being read.
0 R/W Reset by writing 1.
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
S1C17 Core i/O
Remarks
R
R
R
0 R/W
0 R/W
0 R/W
0 R/W Reset by writing 1.
0 R/W
0 R/W
0 R/W
0 R
– – 0 when being read.
– – 0 when being read.
– – 0 when being read.
– – 0 when being read.
aP-a-29