Epson S1C17624 Technical Manual page 344

aPPenDiX a liST OF i/O ReGiSTeRS
0x5300–0x530c
Register name address Bit
T16e Ch.0 0x5300 D15–0 Ca[15:0]
Compare Data
(16 bits)
a Register
(T16e_Ca0)
T16e Ch.0 0x5302 D15–0 CB[15:0]
Compare Data
(16 bits)
B Register
(T16e_CB0)
T16e Ch.0 0x5304 D15–0 TC[15:0]
Counter Data (16 bits)
Register
(T16e_TC0)
T16e Ch.0 0x5306 D15–9 –
Control Register (16 bits)
D8
(T16e_CTl0)
D7
D6
D5
D4
D3
D2
D1
D0
T16e Ch.0 Clock 0x5308 D15–4 –
Division Ratio (16 bits)
D3–0 T16eDF[3:0] Clock division ratio select
Select Register
(T16e_DF0)
T16e Ch.x 0x530a D15–2 –
interrupt Mask
(16 bits)
Register D1
(T16e_iMSKx)
D0
T16e Ch.x 0x530c D15–2 –
interrupt Flag (16 bits) D1
Register
D0
(T16e_iFlGx)
0x4020, 0x5320–0x532c
Register name address Bit
Prescaler 0x4020 D7–2 –
Control Register
(8 bits)
D1
(PSC_CTl)
D0
FlaShC 0x5320 D15–10 –
Control Register
(16 bits) D9–8 –
(MiSC_Fl)
D7–3 –
D2–0 FlCYC[2:0] FLASHC read access cycle
OSC1 Peripheral 0x5322 D15–1 –
Control Register
(16 bits)
D0
(MiSC_OSC1)
aP-a-22
name Function
Compare data A
CA15 = MSB
CA0 = LSB
Compare data B
CB15 = MSB
CB0 = LSB
Counter data
TC15 = MSB
TC0 = LSB
reserved
iniTOl Initial output level
–
reserved
SelFM
Fine mode select
CBuFen
Comparison buffer enable
inVOuT
Inverse output
ClKSel
Input clock select
OuTen
Clock output enable
T16eRST
Timer reset
T16eRun
Timer run/stop control
reserved
reserved
CBie
Compare B interrupt enable
Caie
Compare A interrupt enable
reserved
CBiF Compare B interrupt flag
CaiF
Compare A interrupt flag
name Function
reserved
PRunD
Run/stop select in debug mode
PRun Prescaler run/stop control
reserved
reserved
reserved
reserved
O1DBG
Run/stop select in debug mode
(except PCLK peripheral circuits)
Seiko epson Corporation
16-bit PWM Timer (T16e) Ch.0
Setting init. R/W
0x0 to 0xffff 0x0 R/W
0x0 to 0xffff 0x0 R/W
0x0 to 0xffff 0x0 R/W
–
1 High 0 Low
–
1 Fine mode 0 Normal mode
1 Enable 0 Disable
1 Invert 0 Normal
1 External 0 Internal
1 Enable 0 Disable
1 Reset 0 Ignored
1 Run 0 Stop
–
T16EDF[3:0] Division ratio 0x0 R/W Source clock = PCLK
0xf reserved
0xe
1/16384
0xd
1/8192
0xc
1/4096
0xb
1/2048
0xa
1/1024
0x9
1/512
0x8
1/256
0x7
1/128
0x6
1/64
0x5
1/32
0x4
1/16
0x3
1/8
0x2
1/4
0x1
1/2
0x0
1/1
–
1 Enable 0 Disable
1 Enable 0 Disable
–
1 Cause of 0 Cause of
interrupt interrupt not
occurred occurred
Setting init. R/W
–
1 Run 0 Stop
1 Run 0 Stop
–
– 0x3
–
FLCYC[2:0] Read cycle 0x3 R/W
0x7–0x5 reserved
0x4 1 cycle
0x3 5 cycles
0x2 4 cycles
0x1 3 cycles
0x0 2 cycles
–
1 Run 0 Stop
S1C17624/604/622/602/621 TeChniCal Manual
Remarks
– – 0 when being read.
0 R/W
– – 0 when being read.
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 W 0 when being read.
0 R/W
– – 0 when being read.
– – 0 when being read.
0 R/W
0 R/W
– – 0 when being read.
0 R/W Reset by writing 1.
0 R/W
MiSC Registers
Remarks
– – 0 when being read.
0 R/W
0 R/W
– – 0 when being read.
–
– – 0 when being read.
– – 0 when being read.
0 R/W