Epson S1C17624 Technical Manual page 55

Vector no.
Vector address
Software interrupt no.
16 (0x10) TTBR + 0x40
17 (0x11) TTBR + 0x44
18 (0x12) TTBR + 0x48
19 (0x13) TTBR + 0x4c
20 (0x14) TTBR + 0x50
21 (0x15) TTBR + 0x54
22 (0x16) TTBR + 0x58
23 (0x17) TTBR + 0x5c
24 (0x18) TTBR + 0x60
:
31 (0x1f) TTBR + 0x7c
*1 When the same interrupt level is set
*2 Either reset or NMI can be selected as the watchdog timer interrupt with software.
Vector numbers 4 to 23 are assigned to the maskable interrupts supported by the S1C17624/604/622/602/621.
interrupts that share an interrupt vector
Interrupt vector numbers 7, 10, and 17 are shared with two different interrupt modules.
Interrupt vector 7: Clock timer (CT) and real-time clock (RTC) (S1C17624/604)
Interrupt vector 10: LCD driver (LCD) and 16-bit PWM timer (T16A2) Ch.0 (S1C17624/604)
2
Interrupt vector 17: I
The interrupt signals from the two modules are input to the ITC through an OR gate. When using the two inter-
rupts, check if which interrupt has occurred by reading the interrupt flags in both modules.
The two modules cannot be set to different interrupt level, as they use the same interrupt vector.
Vector table base address
The S1C17624/604/622/602/621 allows the base (starting) address of the vector table to be set using the MISC_
TTBRL and MISC_TTBRH registers. "TTBR" described in Table 6.2.1 means the value set to these registers.
After an initial reset, the MISC_TTBRL and MISC_TTBRH registers are set to 0x8000. Therefore, even when
the vector table location is changed, it is necessary that at least the reset vector be written to the above address.
Bits 7 to 0 in the MISC_TTBRL register are fixed at 0, so the vector table starting address always begins with a
256-byte boundary address.
Vector Table address low/high Registers (MiSC_TTBRl, MiSC_TTBRh)
Register name address Bit
Vector Table 0x5328 D15–8 TTBR[15:8] Vector table base address A[15:8]
address low
(16 bits) D7–0 TTBR[7:0]
Register
(MiSC_TTBRl)
Vector Table 0x532a D15–8 –
address high
(16 bits) D7–0 TTBR[23:16] Vector table base address
Register
(MiSC_TTBRh)
S1C17624/604/622/602/621 TeChniCal Manual
hardware interrupt name
UART Ch.0 interrupt
2
I C Slave (I2CS) interrupt
UART Ch.1 interrupt
SPI Ch.0 interrupt
2
I C Master (I2CM) interrupt
IR remote controller (REMC)
interrupt
16-bit PWM timer (T16A2) Ch.1
interrupt
(S1C17624/604)
A/D converter (ADC10) interrupt
R/F converter (RFC) interrupt
reserved
:
reserved
C slave (I2CS) and UART Ch.1
name Function
Vector table base address A[7:0]
(fixed at 0)
reserved
A[23:16]
Seiko epson Corporation
Cause of hardware interrupt
• Transmit buffer empty
• Receive buffer full
• Receive error
• Transmit buffer empty
• Receive buffer full
• Bus status
• Transmit buffer empty
• Receive buffer full
• Receive error
• Transmit buffer empty
• Receive buffer full
• Transmit buffer empty
• Receive buffer full
• Data length counter underflow
• Input rising edge detected
• Input falling edge detected
• Compare A/B
• Capture A/B
• Capture A/B overwrite
• Conversion completion
• Conversion result overwrite
• Reference oscillation completion
• Sensor A oscillation completion
• Sensor B oscillation completion
• Time base counter overflow error
• Measurement counter overflow error
:
Setting
0x0–0xff
0x0
0x0–0xff
6 inTeRRuPT COnTROlleR (iTC)
–
:
–
init. R/W
0x80 R/W
0x0 R
– – – 0 when being read.
0x0 R/W
Priority
↓
*1
Low
Remarks
6-3