Epson S1C17624 Technical Manual page 227

2
21 i C SlaVe (i2CS)
i 2 C Slave Transmit Data Register (i2CS_TRnS)
Register name address Bit
i 2 C Slave 0x4360 D15–8 –
Transmit Data D7–0 SDaTa[7:0] I
(16 bits)
Register
(i2CS_TRnS)
D[15:8] Reserved
D[7:0] SDaTa[7:0]: i
Sets a transmit data in this register. (Default: 0x0)
The serial-converted data is output from the SDA1 pin beginning with the MSB, in which the bits set to
0 are output as Low-level signals. When the data set in this register is sent to the shift register, a trans-
mit interrupt occurs. The next transmit data can be written to the register after that.
If the clock stretch function has been disabled, data must be written to this register within 7 cycles of
the I 2 C clock (SCL1 input clock) after a transmit interrupt has been occurred.
However, when setting the first transmit data after this module has been selected as the slave device,
follow the precautions described below.
When the clock stretch function is disabled (default)
Transmit data must be written to SDATA[7:0] within 1 cycle of the I
after TXEMP has been set to 1. This time is not enough for data preparation, so write transmit data
before TXEMP has been set to 1. If the previous transmit data is still stored in SDATA[7:0], it is
overwritten with the new data to be transferred. Therefore, the clear operation (see below) using
TBUF_CLR is unnecessary.
When the asynchronous address detection function is used, the data written before ASDET_EN is re-
set to 0 becomes invalid. Therefore, transmission data must be written after TXEMP has been set to 1.
When the clock stretch function is enabled
The master device is placed into wait status by the clock stretch function, so transmit data can be
written after TXEMP is set. However, if the previous transmit data is still stored in SDATA[7:0], it
will be sent immediately after TXEMP has been set. In order to avoid this problem, clear the I2CS_
TRNS register using TBUF_CLR/I2CS_CTL register before this module is selected as the slave
device. The I2CS_TRNS register is cleared by writing 1 to TBUF_CLR then writing 0 to it.
It is not necessary to clear the I2CS_TRNS register if the first transmit data is written before TX-
EMP has been set.
When the asynchronous address detection function is used, the data written before ASDET_EN is re-
set to 0 becomes invalid. Therefore, transmission data must be written after TXEMP has been set to 1.
i 2 C Slave Receive Data Register (i2CS_ReCV)
Register name address Bit
i 2 C Slave 0x4362 D15–8 –
Receive Data D7–0 RDaTa[7:0] I
(16 bits)
Register
(i2CS_ReCV)
D[15:8] Reserved
D[7:0] RDaTa[7:0]: i
The received data can be read from this register. (Default: 0x0)
The serial data input from the SDA1 pin beginning with the MSB is converted into parallel data, with
the high-level signals changed to 1 and the low-level signals changed to 0. The resulting data is stored
in this register.
When a receive operation is completed and the data received in the shift register is loaded to this register,
RXRDY/I2CS_ASTAT register is set and a receive interrupt occurs. Thereafter, the data can be read out.
When the clock stretch function has been disabled, data must be read from this register within 7 cycles
of the I 2 C clock (SCL1 input clock) after RXRDY is set to 1. If the next data has been received without
reading the received data, this register will be overwritten with the newly received data.
21-10
name Function
reserved
2 C slave transmit data
2
C Slave Transmit Data Bits
name Function
reserved
2 C slave receive data
2
C Slave Receive Data Bits
Seiko epson Corporation
Setting init. R/W
– – –
0–0xff 0x0 R/W
2
C clock (SCL1 input clock)
Setting init. R/W
– – –
0–0xff 0x0 R
S1C17624/604/622/602/621 TeChniCal Manual
Remarks
0 when being read.
Remarks
0 when being read.