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Starting clock output
To output the TOUTx and TOUTNx clocks, write 1 to OUTEN/T16E_CTLx register. Writing 0 to OUTEN
switches the output to the initial output level as set by INITOL and INVOUT.
Figure 12.7.2 shows the output waveform.
Compare A signal
Compare B signal
TOUTx output (INITOL = 0, INVOUT = 0)
TOUTx output (INITOL = 0, INVOUT = 1)
TOUTx output (INITOL = 1, INVOUT = 0)
TOUTx output (INITOL = 1, INVOUT = 1)
TOuTx output when inVOuT = 0 (active high)
The TOUTx pin outputs low level (initial output level at output start) until the counter matches the compare
data A set in the T16E_CAx register. When the counter reaches the next compare data A value, the output
pin goes to high level, and a cause of compare A interrupt occurs. If the counter subsequently counts up to
compare data B set in the T16E_CBx register, the counter is reset and the output pin is returned to low level.
A cause of compare B interrupt is also occurred at the same time.
The TOUTNx pin outputs the inverted signals described above.
TOuTx output when inVOuT = 1 (active low)
The TOUTx pin outputs high level (inverted value of the initial output level at output start) until the counter
matches the compare data A set in the T16E_CAx register. When the counter reaches the next compare data
A value, the output pin goes to low level, and a cause of compare A interrupt occurs. If the counter subse-
quently counts up to compare data B set in the T16E_CBx register, the counter is reset and the output pin is
returned to high level. A cause of compare B interrupt is also occurred at the same time.
The TOUTNx pin outputs the inverted signals described above.
Fine mode clock output setting
By default, the clock output changes at the rising edge of the count clock when the counter value matches the
compare data A.
In fine mode, the clock output changes in accordance with the compare data A bit 0 (CA0) value when the counter
data register TC[14:0] matches the compare data A register CA[15:1].
When CA0 is 0: Changes at the rising edge of the count clock.
When CA0 is 1: Changes at the half-cycle delayed falling edge of the count clock.
S1C17624/604/622/602/621 TeChniCal Manual
Table 12.
7.1 Initial Output Level
iniTOl
1
1
0
0
Count clock
T16ERST
OUTEN
T16ERUN
0
Counter value
Figure 12.
7.2 T16E Output Waveform
Seiko epson Corporation
inVOuT
initial output level
1
Low
0
High
1
High
0
Low
1 2 3 4 5 0
1
(When T16E_CAx = 3, T16E_CBx = 5)
12 16-BiT PWM TiMeR (T16e)
2 3 4 5 0 1 2 3 4 5 0 1
12-5
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