Epson S1C17624 Technical Manual page 99

D[7:0] PxPu[7:0]: Px[7:0] Port Pull-up enable Bits
Enables or disables the pull-up resistor included in each port.
1 (R/W): Enabled (default)
0 (R/W): Disabled
PxPUy is the pull-up control bit that corresponds directly to the Pxy port. Setting to 1 enables the pull-
up resistor and the port pin will be pulled up when output is disabled (PxOENy = 0). When PxPUy is set
to 0, the pin will not be pulled up.
When output is enabled (PxOENy = 1), the PxPUy setting is ignored, and the pin is not pulled up.
I/O ports that are not used should be set with pull-up enabled.
This pull-up setting is also enabled for ports for which the peripheral module input function is selected.
Px Port Schmitt Trigger Control Registers (Px_SM)
Register name address Bit
P0 Port Schmitt 0x5204 D7–0 P0SM[7:0]
Trigger Control (8 bits)
Register
(P0_SM)
P1 Port Schmitt 0x5214 D7–6 P1SM[7:6]
Trigger Control (8 bits)
Register D5–0 P1SM[5:0]
(P1_SM)
P2 Port Schmitt 0x5224 D7–0 P2SM[7:0]
Trigger Control
(8 bits)
Register
(P2_SM)
P3 Port Schmitt 0x5234 D7–0 P3SM[7:0]
Trigger Control
(8 bits)
Register
(P3_SM)
P4 Port Schmitt 0x5244 D7–4 P4SM[7:4]
Trigger Control (8 bits)
Register D3–0 P4SM[3:0]
(P4_SM)
P5 Port Schmitt 0x5254
D7
Trigger Control (8 bits)
D6–3 P5SM[6:3]
Register
(P5_SM)
D2–0 P5SM[2:0]
(S1C17624/622)
note: The PxSMy bits for unavailable ports are reserved and always read as 0.
D[7:0] PxSM[7:0]: Px[7:0] Port Schmitt Trigger input enable Bits
Enables or disables the Schmitt trigger input buffer for each port.
1 (R/W): Enable (Schmitt) (default)
0 (R/W): Disable (CMOS level)
PxSMy is the Schmitt input control bit that corresponds directly to the Pxy port. Setting to 1 enables the
Schmitt input buffer, and setting to 0 uses the CMOS level input buffer.
The I/O ports shown below support only CMOS Schmitt input.
S1C17624/622: P1[7:6], P2[7:0], P3[7:0], P40, DSIO/P41, DST2/P42, DCLK/P43*, P5[6:3]
S1C17604/602/621: P1[7:6], P2[7:0], P3[7:0], P40, DSIO/P41, DST2/P42, DCLK/P43*
In the S1C17624/622/604, the PxSMy bits for these ports are read-only bits that are always read as 1. In
the S1C17602/621, both 1 and 0 can be written to and read from these bits. However, the input interface
level cannot be switched.
Px Port interrupt Mask Registers (Px_iMSK)
Register name address Bit
Px Port 0x5205 D7–0 Pxie[7:0]
interrupt Mask 0x5215
Register (8 bits)
(Px_iMSK)
S1C17624/604/622/602/621 TeChniCal Manual
name Function
P0[7:0] port Schmitt trigger input
enable
P1[7:6] port Schmitt trigger input
enable
P1[5:0] port Schmitt trigger input
enable
P2[7:0] port Schmitt trigger input
enable
P3[7:0] port Schmitt trigger input
enable
P4[7:4] port Schmitt trigger input
enable
P4[3:0] port Schmitt trigger input
enable
–
reserved
P5[6:3] port Schmitt trigger input
enable
P5[2:0] port Schmitt trigger input
enable
name Function
Px[7:0] port interrupt enable
Seiko epson Corporation
Setting init. R/W
1 Enable 0 Disable
(Schmitt) (CMOS)
1 Enable 0 –
(Schmitt)
1 Enable 0 Disable
(Schmitt) (CMOS)
1 Enable 0 –
(Schmitt)
1 Enable 0 –
(Schmitt)
1 Enable 0 Disable
(Schmitt) (CMOS)
1 Enable 0 –
(Schmitt)
–
1 Enable 0 –
(Schmitt)
1 Enable 0 Disable
(Schmitt) (CMOS)
(* P43 is an output-only port.)
Setting init. R/W
1 Enable 0 Disable
9 i/O PORTS (P)
Remarks
1 R/W
1 R Always enabled
1 R/W
1 R Always enabled
1 R Always enabled
1 R/W D[7:4] = reserved in
S1C17604/602/621
1 R Always enabled
– – 0 when being read.
1 R Always enabled
1 R/W
Remarks
0 R/W
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