I2Cs: Timing Charts; I2Cs: Bus Status Interrupt - Epson S1C17624 Technical Manual

If a stop condition is detected while the I2CS module is selected as the slave device (SELECTED = 1), the
I2CS module sets DA_STOP/I2CS_STAT register to 1. At the same time, it sets the SDA1 and SCL1 pins into
high-impedance and initializes the I
next start condition. Also SELECTED and BUSY are reset to 0.
An interrupt can be generated when DA_STOP is set to 1, so a communication terminating process should be
performed in the interrupt handler routine. DA_STOP is cleared by writing 1.
Disabling data transfer
After data transfer has finished, write 0 to the COM_MODE/I2CS_CTL register to disable data transfer.
Always make sure that BUSY and SELECTED are 0 before disabling data transfer.
To deactivate the I2CS module, set I2CSEN/I2CS_CTL register to 0.
Timing charts
Start condition
PCLK
SCL1 (input)
SCL1 (output)
SDA1 (input)
SDA1 (output)
R/W
BUSY
SELECTED
TXEMP
TXUDF
DA_NAK
DA_STOP
Transmit data shift register
SDATA[7:0]
Interrupt
Figure 21.
Data transmission
PCLK
SCL1 (input)
SCL1 (output)
SDA1 (input)
SDA1 (output) D0'
R/W
BUSY
SELECTED
TXEMP
TXUDF
DA_NAK
DA_STOP
Transmit data shift register shift
SDATA[7:0]
Interrupt
Figure 21.
S1C17624/604/622/602/621 TeChniCal Manual
SDA1 (input)
SCL1 (input)
Figure 21.
2
C communication process to enter standby state that is ready to detect the
Slave address reception
A6 A5 A4 A3
5.5 I2CS Timing Chart 1 (start condition → data transmission)
Clock stretch
PCLK x 6
ACK
D0' D7 D6
valid shift
Transmit interrupt
Transmit data is set.
5.6 I2CS Timing Chart 2 (data transmission → stop condition)
Seiko epson Corporation
Stop condition
5.4 Stop Condition
A2 A1 A0 R/W = 1
Data transmission
D5 D4 D3 D2
shift shift shift shift
D[7:0]
2
21 i C SlaVe (i2CS)
Clock stretch Data transmission
PCLK x 6
ACK H/L D7
valid
D[7:0]
Transmit interrupt Transmit interrupt
Transmit data is set.
Stop condition
NAK
D1 D0
shift shift
Bus status interrupt
D6
shift
21-7