Epson S1C17624 Technical Manual page 221

2
21 i C SlaVe (i2CS)
enabling data transfers
First, set I2CSEN/I2CS_CTL register to 1 to enable I2CS operation. This makes the I2CS in ready-to-transmit/
receive status in which a start condition can be detected.
note: Do not set the I2CSEN bit to 0 while the I2CS module is transmitting/receiving data.
Starting data transfer
To start data transmission/reception, set COM_MODE/I2CS_CTL register to 1 to enable data communications.
When the slave address for this module that has been sent from the master is received after a start condition is
detected, the I2CS module returns an ACK (SDA1 = low) and starts operating for data reception or data trans-
mission according to the transfer direction bit that has been received with the slave address.
When COM_MODE is 0 (default), the I2CS module does not send back a response if the master has sent the
slave address of this module (it is regarded as that the I2CS module has returned a NAK to the master).
SDA1 (input)
SDA1 (output)
SCL1 (input)
Start condition
When a start condition is detected, BUSY/I2CS_ASTAT register is set to 1 to indicate that the I
into busy status. When the slave address of this module is received, SELECTED/I2CS_ASTAT register is set
to 1 to indicate that this module has been selected as the I
condition is detected. SELECTED is maintained at 1 until a stop condition or repeated start condition is de-
tected.
The value of the transfer direction bit is set to R/W/I2CS_ASTAT register, so use R/W to select the transmit- or
receive-handling.
If the slave address of this module is detected when the asynchronous address detection function has been en-
abled, ASDET/I2CS_STAT register is set to 1. The I2CS module generates a bus status interrupt and returns
NAK to the I 2 C master to request for resending the slave address. Set the PCLK frequency to eight-times or
higher than the transfer rate and disable the asynchronous address detection function in the interrupt handler
routine. Data transfer will be able to resume normally after the master retries transmission. ASDET can be
cleared by writing 1.
Data transmission
The following describes a data transmission procedure.
The I2CS module starts data transmission process when both SELECTED and R/W are set to 1. It sets TXEMP/
I2CS_ASTAT register to 1 to issue a request to the application program to write transmit data. Write transmit
data to SDATA[7:0]/I2CS_TRNS register.
When setting the first transmit data after this module has been selected as the slave device, follow the precau-
tions described below.
When the clock stretch function is disabled (default)
Transmit data must be written to SDATA[7:0] within 1 cycle of the I
EMP has been set to 1. This time is not enough for data preparation, so write transmit data before TXEMP
has been set to 1. If the previous transmit data is still stored in SDATA[7:0], it is overwritten with the new
data to be transferred. Therefore, the clear operation (see below) using TBUF_CLR is unnecessary.
21-4
7-bit slave address
D7 D6 D5 D4
A6 A5 A4 A3
1 2 3 4
Figure 21. 5.1 Receiving Slave Address and Data Direction Bit
Seiko epson Corporation
Transfer direction
0: master → slave (data reception)
1: slave → master (data transmission)
D3 D2 D1 D0
A2 A1 A0 R/W
ACK
NAK
5 6 7 8 9
2
C slave device. BUSY is maintained at 1 until a stop
2 C clock (SCL1 input clock) after TX-
S1C17624/604/622/602/621 TeChniCal Manual
2
C bus is put