Epson S1C17624 Technical Manual page 257

23 lCD DRiVeR (lCD)
23.7 lCD interrupt
The LCD module includes a function for generating interrupts using the frame signal.
Frame interrupt
This cause of interrupt occurs every frame and sets the interrupt flag FRMIF/LCD_IFLG register in the LCD
module to 1. See Figures 23.4.2.1 to 23.4.2.5 for interrupt timings.
To use this interrupt, set FRMIE/LCD_IMSK register to 1. When FRMIE is set to 0 (default), interrupt requests
for this interrupt cause are not sent to the interrupt controller (ITC).
If FRMIF is set to 1 while FRMIE is set to 1 (interrupt enabled), the LCD module outputs an interrupt request
to the ITC. An interrupt is generated if the ITC and S1C17 Core interrupt conditions are satisfied.
For more information on interrupt processing, see the "Interrupt Controller (ITC)" chapter.
notes: • To prevent interrupt recurrences, the LCD module interrupt flag FRMIF must be reset in the
interrupt handler routine after an LCD interrupt has occurred.
• To prevent unwanted interrupts, FRMIF should be reset before enabling LCD interrupts with
FRMIE.
23.8 Control Register Details
address
0x5063 OSC_LCLK LCD Clock Select Register
0x50a0 LCD_DCTL LCD Display Control Register
0x50a1 LCD_CADJ LCD Contrast Adjustment Register
0x50a2 LCD_CCTL LCD Clock Control Register
0x50a3 LCD_VREG LCD Voltage Regulator Control Register
0x50a5 LCD_IMSK LCD Interrupt Mask Register
0x50a6 LCD_IFLG LCD Interrupt Flag Register
The LCD module registers are described in detail below. These are 8-bit registers.
note: When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1.
lCD Clock Select Register (OSC_lClK)
Register name address Bit
lCD Clock 0x5063 D7–5 –
Select Register
(8 bits) D4–2 lCKDV[2:0] LCD clock division ratio select
(OSC_lClK)
D1
D0
D[7:5] Reserved
D[4:2] lCKDV[2:0]: lCD Clock Division Ratio Select Bits
Selects the division ratio when HSCLK (IOSC or OSC3) is selected as the LCD clock source.
23-14
Table 23. 8.1 List of LCD Registers
Register name
name Function
reserved
lCKSRC
LCD clock source select
lCKen LCD clock enable
Seiko epson Corporation
Function
Selects the LCD clock.
Controls the LCD display.
Controls the contrast.
Controls the LCD drive duty.
Controls the LCD drive voltage regulator.
Enables/disables interrupts.
Indicates/resets interrupt occurrence status.
Setting
–
LCKDV[2:0] Division ratio
0x7–0x5 reserved
0x4 1/512
0x3 1/256
0x2 1/128
0x1 1/64
0x0 1/32
1 OSC1 0 HSCLK
1 Enable 0 Disable
S1C17624/604/622/602/621 TeChniCal Manual
init. R/W Remarks
– – 0 when being read.
0x0 R/W When the clock
source is HSCLK
1 R/W
0 R/W