Transfer Source End Pointer; Transfer Destination End Pointer; Control Data - Epson S1C31D50 Technical Manual

Alternate data structure
Ch.31 (alternate)
0x3f0
Ch.30 (alternate)
0x3e0
Ch.29 (alternate)
0x3d0
Ch.28 (alternate)
0x3c0
Ch.27 (alternate)
0x3b0
Ch.26 (alternate)
0x3a0
Ch.25 (alternate)
0x390
Ch.24 (alternate)
0x380
Ch.23 (alternate)
0x370
Ch.22 (alternate)
0x360
Ch.21 (alternate)
0x350
Ch.20 (alternate)
0x340
Ch.19 (alternate)
0x330
Ch.18 (alternate)
0x320
Ch.17 (alternate)
0x310
Ch.16 (alternate)
0x300
Ch.15 (alternate)
0x2f0
Ch.14 (alternate)
0x2e0
Ch.13 (alternate)
0x2d0
Ch.12 (alternate)
0x2c0
Ch.11 (alternate)
0x2b0
Ch.10 (alternate)
0x2a0
Ch.9 (alternate)
0x290
Ch.8 (alternate)
0x280
Ch.7 (alternate)
0x270
Ch.6 (alternate)
0x260
Ch.5 (alternate)
0x250
Ch.4 (alternate)
0x240
Ch.3 (alternate)
0x230
Ch.2 (alternate)
0x220
Ch.1 (alternate)
0x210
Ch.0 (alternate)
0x200
Base address set with the DMACCPTR register
Figure 6.4.1 Data Structure Address Map (when 32 channels are implemented)
Alternate data structure
Ch.3 (alternate)
0x070
Ch.2 (alternate)
0x060
Ch.1 (alternate)
0x050
Ch.0 (alternate)
0x040
Base address set with the DMACCPTR register
Figure 6.4.2 Data Structure Address Map (when 4 channels are implemented)
The alternate data structure base address can be determined from the DMACACPTR.ACPTR[31:0] bits.

6.4.1 Transfer Source End Pointer

Set the source data end address. The address of data to be transferred should be set as it is if the transfer source ad-
dress is not incremented.

6.4.2 Transfer Destination End Pointer

Set the address to which the last transfer data is written. The address for writing transfer data should be set as it is if
the transfer destination address is not incremented.
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Primary data structure
Ch.31 (primary)
0x1f0
Ch.30 (primary)
0x1e0
Ch.29 (primary)
0x1d0
Ch.28 (primary)
0x1c0
Ch.27 (primary)
0x1b0
Ch.26 (primary)
0x1a0
Ch.25 (primary)
0x190
Ch.24 (primary)
0x180
Ch.23 (primary)
0x170
Ch.22 (primary)
0x160
Ch.21 (primary)
0x150
Ch.20 (primary)
0x140
Ch.19 (primary)
0x130
Ch.18 (primary)
0x120
Ch.17 (primary)
0x110
Ch.16 (primary)
0x100
Ch.15 (primary)
0x0f0
Ch.14 (primary)
0x0e0
Ch.13 (primary)
0x0d0
Ch.12 (primary)
0x0c0
Ch.11 (primary)
0x0b0
Ch.10 (primary)
0x0a0
Ch.9 (primary)
0x090
Ch.8 (primary)
0x080
Ch.7 (primary)
0x070
Ch.6 (primary)
0x060
Ch.5 (primary)
0x050
Ch.4 (primary)
0x040
Ch.3 (primary)
0x030
Ch.2 (primary)
0x020
Ch.1 (primary)
0x010
Ch.0 (primary)
0x000
Offset
Primary data structure
Ch.3 (primary)
0x030
Ch.2 (primary)
0x020
Ch.1 (primary)
0x010
Ch.0 (primary)
0x000
Offset
Seiko Epson Corporation
6 DMA CONTROLLER (DMAC)
Reserved

Control data

Transfer destination end pointer
Transfer source end pointer
Reserved
Control data
Transfer destination end pointer
Transfer source end pointer
0x00c
0x008
0x004
0x000
0x00c
0x008
0x004
0x000
6-3