Pd Port Group - Epson S1C31D50 Technical Manual

Cmos 32-bit single chip
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Register name
Bit
PAMODSEL
15–8 –
(Pa Port Mode Select
7
Register)
6
5
4
3
2
1
0
PAFNCSEL
15–14 –
(Pa Port Function
13–12 PA6MUX[1:0]
Select Register)
11–10 PA5MUX[1:0]
9–8 PA4MUX[1:0]
7–6 PA3MUX[1:0]
5–4 PA2MUX[1:0]
3–2 PA1MUX[1:0]
1–0 PA0MUX[1:0]
PASELy = 0
Port
PAyMUX = 0x0
name
GPIO
(Function 0)
Peripheral
Pa0
Pa0
Pa1
Pa1
Pa2
Pa2
Pa3
Pa3
CLG
Pa4
Pa4
Pa5
Pa5
Pa6
Pa6

7.7.12 Pd Port Group

The Pd port group support the GPIO function. The Pd0 and Pd1 ports are configured as debugging function ports at
initialization.
Register name
Bit
PDDAT
15–14 –
(Pd Port Data
13
Register)
12
11
10
9
8
7–6 –
5
4
3
2
1
0
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Bit name
Initial
0x00
0
PASEL6
0
PASEL5
0
PASEL4
0
PASEL3
0
PASEL2
0
PASEL1
0
PASEL0
0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Table 7.7.11.2 Pa Port Group Function Assignment
PAyMUX = 0x1
(Function 1)
Pin
Peripheral
FOUT
Table 7.7.12.1 Control Registers for Pd Port Group
Bit name
Initial
0x0
PDOUT5
0
PDOUT4
0
PDOUT3
0
PDOUT2
0
PDOUT1
0
PDOUT0
0
0x0
PDIN5
0
PDIN4
0
PDIN3
0
PDIN2
0
PDIN1
0
PDIN0
0
Seiko Epson Corporation
Reset
R/W
R
R
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
R
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
PASELy = 1
PAyMUX = 0x2
(Function 2)
Pin
Peripheral
Pin
Reset
R/W
R
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
R
H0
R
H0
R
H0
R
H0
R
H0
R
H0
R
7 I/O PORTS (PPORT)
48
64
Remarks
pin
pin
PAyMUX = 0x3
48
64
(Function 3)
pin
pin
Peripheral
Pin
48
64
Remarks
pin
pin
80
100
pin
pin
80
100
pin
pin
80
100
pin
pin
7-37

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