Qspi Ch.n Remapping Start Address High Register; Qspi Ch.n Memory Mapped Access Configuration Register 2 - Epson S1C31D50 Technical Manual

QSPI Ch.n Remapping Start Address High Register

Register name Bit
QSPI_nRMADRH 15–4 RMADR[31:20]
3-0 –
Bits 15–4 RMADR[31:20]
These bits specify the high-order 12 bits of the external Flash memory area start address (assumed as
32 bits) to be remapped to the system memory area allocated for memory mapped access mode. When
the external Flash memory is read using the memory mapped access function, the value specified here
is added, as an offset, to the relative address in the memory mapped access area to generate the exter-
nal Flash memory address to actually be accessed.
Note: Make sure the QSPI_nMMACFG2.MMAEN = 0 when altering the QSPI_nRMADRH.
RMADR[31:20] bits.
Memory mapped
access area
Bits 3–0 Reserved

QSPI Ch.n Memory Mapped Access Configuration Register 2

Register name Bit
QSPI_nMMACFG2 15–12 DUMDL[3:0]
11–8 DUMLN[3:0]
7–6 DATTMOD[1:0]
5–4 DUMTMOD[1:0]
3–2 ADRTMOD[1:0]
1
0
Bits 15–12 DUMDL[3:0]
These bits set the number of clocks for driving the serial data lines during the dummy cycle output
when accessing the external Flash memory in the memory mapped access mode. This setting is re-
quired to output the XIP confirmation bit to Micron Flash memories or to output the mode byte to
Spansion Flash memories.
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Bit name Initial
0x000
0x0
C31 system memory
Figure 15.8.1 External Flash Memory Remapping
Bit name Initial
0x0
0x0
0x0
0x0
0x0
ADRCYC 0
MMAEN 0
Seiko Epson Corporation
15 Quad Synchronous Serial Interface (QSPI)
Reset R/W
H0 R/W –
– R
External flash memory
0x N fffff
RMADR = N
0x N 00000
0x000fffff
RMADR = 0
0x00000000
(N = QSPI_nRMADRH.RMADR[31:20] setting value)
Reset R/W
H0 R/W –
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
Remarks
Offset = N
Remarks
15-35