Epson S1C31D50 Technical Manual page 215

15 Quad Synchronous Serial Interface (QSPI)
Bits 7–6 TMOD[1:0]
These bits select a transfer mode.
QSPI_nMOD.
TMOD[1:0] bits
Bit 5 PUEN
This bit enables pull-up/down of the pins that are configured as an input or are not used.
1 (R/W): Enable pull-up/down
0 (R/W): Disable pull-up/down
For more information, refer to "Input Pin Pull-Up/Pull-Down Function."
Bit 4 NOCLKDIV
This bit selects QSPICLKn in master mode. This setting is ineffective in slave mode.
1 (R/W): QSPICLKn frequency = CLK_QSPIn frequency ( = 16-bit timer operating clock frequency)
0 (R/W): QSPICLKn frequency = 16-bit timer output frequency / 2
For more information, refer to "QSPI Operating Clock."
Bit 3 LSBFST
This bit configures the data format (input/output permutation).
1 (R/W): LSB first
0 (R/W): MSB first
Bit 2 CPHA
Bit 1 CPOL
These bits set the QSPI clock phase and polarity. For more information, refer to "QSPI Clock (QSPI-
CLKn) Phase and Polarity."
15-30
Table 15.8.2 Setting of Number of Data Transfer Clocks
QSPI_nMOD.CHLN[3:0] bits
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Table 15.8.3 Transfer Mode
0x3 Reserved
0x2 Quad transfer mode
The QSDIOn[3:0] pins are configured as input or out-
put pins according to the QSPI_nMOD.DIR bit setting.
0x1 Dual transfer mode
The QSDIOn[1:0] pins are configured as input or out-
put pins according to the QSPI_nMOD.DIR bit setting.
The QSDIOn[3:2] pins are not used.
0x0 Single transfer mode
The QSDIOn0 and QSDIOn1 pins are configured as an
output pin and an input pin, respectively.
The QSDIOn[3:2] pins are not used.
Seiko Epson Corporation
Number of data transfer clocks
16 clocks
15 clocks
14 clocks
13 clocks
12 clocks
11 clocks
10 clocks
9 clocks
8 clocks
7 clocks
6 clocks
5 clocks
4 clocks
3 clocks
2 clocks
Setting prohibited
Transfer mode
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)