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7 I/O PORTS (PPORT)
Bits 7–0
PxOEN[7:0]
These bits enable/disable the GPIO port output.
1 (R/W): Enable (Data is output from the port pin.)
0 (R/W): Disable (The port is placed into Hi-Z.)
These bits do not affect the output control when the port is used as a peripheral I/O function.
Px Port Pull-up/down Control Register
Register name
Bit
PPORTPxRCTL
15–8 PxPDPU[7:0]
7–0 PxREN[7:0]
*1: This register is effective when the GPIO function is selected.
*2: The bit configuration differs depending on the port group.
Bits 15–8 PxPDPU[7:0]
These bits select either the pull-up resistor or the pull-down resistor when using a resistor built into
the port.
1 (R/W): Pull-up resistor
0 (R/W): Pull-down resistor
The selected pull-up/down resistor is enabled when the PPORTPxRCTL.PxRENy bit = 1.
Bits 7–0
PxREN[7:0]
These bits enable/disable the port pull-up/down control.
1 (R/W): Enable (The built-in pull-up/down resistor is used.)
0 (R/W): Disable (No pull-up/down control is performed.)
Enabling this function pulls up or down the port when output is disabled (PPORTPxIOEN.PxOENy
bit = 0). When output is enabled (PPORTPxIOEN.PxOENy bit = 1), the PPORTPxRCTL.PxRENy bit
setting is ineffective regardless of how the PPORTPxIOEN.PxIENy bit is set and the port is not pulled
up/down. These bits do not affect the pull-up/down control when the port is used as a peripheral I/O
function.
Px Port Interrupt Flag Register
Register name
Bit
PPORTPxINTF
15–8 –
7–0 PxIF[7:0]
*1: This register is effective when the GPIO function is selected.
*2: The bit configuration differs depending on the port group.
Bits 15–8 Reserved
Bits 7–0
PxIF[7:0]
These bits indicate the port input interrupt cause occurrence status.
1 (R):
Cause of interrupt occurred
0 (R):
No cause of interrupt occurred
1 (W):
Clear flag
0 (W):
Ineffective
Px Port Interrupt Control Register
Register name
Bit
PPORTPxINTCTL
15–8 PxEDGE[7:0]
7–0 PxIE[7:0]
*1: This register is effective when the GPIO function is selected.
*2: The bit configuration differs depending on the port group.
Bits 15–8 PxEDGE[7:0]
These bits select the input signal edge to generate a port input interrupt.
1 (R/W): An interrupt will occur at a falling edge.
0 (R/W): An interrupt will occur at a rising edge.
7-8
Bit name
Initial
0x00
0x00
Bit name
Initial
0x00
0x00
Bit name
Initial
0x00
0x00
Seiko Epson Corporation
Reset
R/W
H0
R/W
–
H0
R/W
Reset
R/W
–
R
–
H0
R/W
Cleared by writing 1.
Reset
R/W
H0
R/W
–
H0
R/W
S1C31D50/D51 TECHNICAL MANUAL
Remarks
Remarks
Remarks
(Rev. 2.00)
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