Data Transmission In Master Mode - Epson S1C31D50 Technical Manual

16.4.2 Data Transmission in Master Mode

A data sending procedure in master mode and the I2C Ch.n operations are shown below. Figures 16.4.2.1 and 16.4.2.2
show an operation example and a flowchart, respectively.
Data sending procedure
1. Issue a START condition by setting the I2C_nCTL.TXSTART bit to 1.
2. Wait for a transmit buffer empty interrupt (I2C_nINTF.TBEIF bit = 1) or a START condition interrupt (I2C_
nINTF.STARTIF bit = 1).
Clear the I2C_nINTF.STARTIF bit by writing 1 after the interrupt has occurred.
3. Write the 7-bit slave address to the I2C_nTXD.TXD[7:1] bits and 0 that represents WRITE as the data trans-
fer direction to the I2C_nTXD.TXD0 bit.
4. (When DMA is used) Configure the DMA controller and set a DMA transfer request enable bit in the I2C_
nTBEDMAEN register to 1 (DMA transfer request enabled). (This automates the data sending procedure
Steps 5, 6, and 8.)
5. (When DMA is not used) Wait for a transmit buffer empty interrupt (I2C_nINTF.TBEIF bit = 1) generated
when an ACK is received.
6. (When DMA is not used) Write transmit data to the I2C_nTXD register.
7. If a NACK reception interrupt (I2C_nINTF.NACKIF bit = 1) has occurred, go to Step 9 or 1 after clearing
the I2C_nINTF.NACKIF bit.
8. (When DMA is not used) Repeat Steps 5 and 6 until the end of transmit data.
9. Issue a STOP condition by setting the I2C_nCTL.TXSTOP bit to 1.
10. Wait for a STOP condition interrupt (I2C_nINTF.STOPIF bit = 1).
Clear the I2C_nINTF.STOPIF bit by writing 1 after the interrupt has occurred.
Data sending operations
Generating a START condition
The I2C Ch.n starts generating a START condition when the I2C_nCTL.TXSTART bit is set to 1. When the
generating operation has completed, the I2C Ch.n clears the I2C_nCTL.TXSTART bit to 0 and sets both the
I2C_nINTF.STARTIF and I2C_nINTF.TBEIF bits to 1.
Sending slave address and data
If the I2C_nINTF.TBEIF bit = 1, a slave address or data can be written to the I2C_nTXD register. The I2C
Ch.n pulls down SCL to low and enters standby state until data is written to the I2C_nTXD register. The
writing operation triggers the I2C Ch.n to send the data to the shift register automatically and to output
eight clock pulses and data bits to the I
When the slave device returns an ACK as the response, the I2C_nINTF.TBEIF bit is set to 1. After this
interrupt occurs, the subsequent data may be sent or a STOP/repeated START condition may be issued to
terminate transmission. If the slave device returns NACK, the I2C_nINTF.NACKIF bit is set to 1 without
setting the I2C_nINTF.TBEIF bit.
Generating a STOP/repeated START condition
After the I2C_nINTF.TBEIF bit is set to 1 (transmit buffer empty) or the I2C_nINTF.NACKIF bit is set to 1
(NACK received), setting the I2C_nCTL.TXSTOP bit to 1 generates a STOP condition. When the bus free
time (t defined in the I
BUF
I2C_nCTL.TXSTOP bit is cleared to 0 and the I2C_nINTF.STOPIF bit is set to 1.
When setting the I2C_nCTL.TXSTART bit to 1 while the I2C_nINTF.TBEIF bit = 1 (transmit buffer emp-
ty) or the I2C_nINTF.NACKIF bit = 1 (NACK received), the I2C Ch.n generates a repeated START condi-
tion. When the repeated START condition has been generated, the I2C_nINTF.STARTIF and I2C_nINTF.
TBEIF bits are both set to 1 same as when a START condition has been generated.
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
2 C bus.
2 C Specifications) has elapsed after the STOP condition has been generated, the
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16 I C (I2C)
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