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Compare period and count cycle settings using DMA
By setting the T16B_nCCmDMAEN.CCmDMAENx bit to 1 (DMA transfer request enabled) in compara-
tor mode, a DMA transfer request is sent to the DMA controller and compare data is transferred from the
specified memory to the T16B_nCCRm register via DMA Ch.x when the T16B_nINTF.CMPCAPmIF bit is
set to 1 (when the counter reaches the compare buffer value).
Similarly, by setting the T16B_nCCmDMAEN.MZDMAENx bit to 1 (DMA transfer request enabled),
a DMA transfer request is sent to the DMA controller and a counter MAX value is transferred from the
specified memory to the T16B_nMC register via DMA Ch.x when the T16B_nINTF.CNTMAXIF bit is set
to 1 (when the counter reaches the MAX value) in up or up/down count mode, or when the T16B_nINTF.
CNTZEROIF bit is set to 1 (when the counter reaches zero) in down count mode.
This automates the compare period and count cycle settings of the timer counter.
The transfer source/destination and control data must be set for the DMA controller and the relevant DMA
channel must be enabled to start a DMA transfer in advance so that the setting data will be transferred to the
T16B_nCCRm or T16B_nMC register. For more information on DMA, refer to the "DMA Controller" chap-
ter.
Table 17.4.3.1 DMA Data Structure Configuration Example (T16B Compare Period and Count Cycle Settings)
End pointer
Transfer source
Transfer destination T16B_nCCRm or T16B_nMC register address
Control data dst_inc
dst_size
src_inc
src_size
R_power
n_minus_1
cycle_ctrl
Operations in capture mode
The capture mode captures the counter value when an external event, such as a key entry, occurs (at the speci-
fied edge of the external input/software trigger signal). In this mode, the T16B_nCCRm register functions as
the capture register from which the captured data is read. Furthermore, the TOUTnm/CAPnm pin is configured
to the CAPnm pin.
The trigger signal and the trigger edge to capture the counter value are selected using the T16B_nCCCTLm.
CAPIS[1:0] bits and the T16B_nCCCTLm.CAPTRG[1:0] bits, respectively.
When a specified trigger edge is input during counting, the current counter value is loaded to the T16B_nC-
CRm register. At the same time the T16B_nINTF.CMPCAPmIF bit is set. The interrupt occurred by this bit can
be used to read the captured data from the T16B_nCCRm register. For example, external event cycles and pulse
widths can be measured from the difference between two captured counter values read.
If the captured data stored in the T16B_nCCRm register is overwritten by the next trigger when the T16B_
nINTF.CMPCAPmIF bit is still set, an overwrite error occurs (the T16B_nINTF.CAPOWmIF bit is set).
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Item
Memory address in which the last setting data is stored
0x3 (no increment)
0x1 (haflword)
0x1 (+2)
0x1 (halfword)
0x0 (arbitrated for every transfer)
Number of transfer data
0x1 (basic transfer)
Seiko Epson Corporation
17 16-BIT PWM TIMERS (T16B)
Setting example
17-15
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