Spia Ch.n Interrupt Enable Register; Spia Ch.n Transmit Buffer Empty Dma Request Enable Register; Spia Ch.n Receive Buffer Full Dma Request Enable Register - Epson S1C31D50 Technical Manual

14 SYNCHRONOUS SERIAL INTERFACE (SPIA)
The following shows the correspondence between the bit and interrupt:
SPIA_nINTF.OEIF bit:
SPIA_nINTF.TENDIF bit: End-of-transmission interrupt
SPIA_nINTF.RBFIF bit: Receive buffer full interrupt
SPIA_nINTF.TBEIF bit: Transmit buffer empty interrupt

SPIA Ch.n Interrupt Enable Register

Register name Bit
SPIA_nINTE 15–8 –
7–4 –
3
2
1
0
Bits 15–4 Reserved
Bit 3 OEIE
Bit 2 TENDIE
Bit 1 RBFIE
Bit 0 TBEIE
These bits enable SPIA interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
The following shows the correspondence between the bit and interrupt:
SPIA_nINTE.OEIE bit:
SPIA_nINTE.TENDIE bit: End-of-transmission interrupt
SPIA_nINTE.RBFIE bit: Receive buffer full interrupt
SPIA_nINTE.TBEIE bit: Transmit buffer empty interrupt

SPIA Ch.n Transmit Buffer Empty DMA Request Enable Register

Register name Bit
SPIA_nTBEDMAEN 15–0 TBEDMAEN[15:0]
Bits 15–0 TBEDMAEN[15:0]
These bits enable the SPIA to issue a DMA transfer request to the corresponding DMA channel (Ch.0–
Ch.15) when a transmit buffer empty state has occurred.
1 (R/W): Enable DMA transfer request
0 (R/W): Disable DMA transfer request
Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan-
nels are ineffective.

SPIA Ch.n Receive Buffer Full DMA Request Enable Register

Register name Bit
SPIA_nRBFDMAEN 15–0 RBFDMAEN[15:0]
Bits 15–0 RBFDMAEN[15:0]
These bits enable the SPIA to issue a DMA transfer request to the corresponding DMA channel (Ch.0–
Ch.15) when a receive buffer full state has occurred.
1 (R/W): Enable DMA transfer request
0 (R/W): Disable DMA transfer request
Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan-
nels are ineffective.
14-16
Overrun error interrupt
Bit name Initial
0x00
0x0
OEIE 0
TENDIE 0
RBFIE 0
TBEIE 0
Overrun error interrupt
Bit name Initial
0x0000
Bit name Initial
0x0000
Seiko Epson Corporation
Reset R/W
– R –
– R
H0 R/W
H0 R/W
H0 R/W
H0 R/W
Reset R/W
H0 R/W –
Reset R/W
H0 R/W –
S1C31D50/D51 TECHNICAL MANUAL
Remarks
Remarks
Remarks
(Rev. 2.00)