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23 Basic External Connection Diagram
1.8–5.5 V,
+
∗1
C
2.4–5.5 V
,
PW1
∗2
or 2.7–5.5 V
C
PW2
+
3.0–3.6 V
C
VDDQSPI
∗3
(
)
C
G1
( )
X'tal1
C
D1
∗4
( )
C
G3
( )
X'tal3/
C
D3
Ceramic
*1: For Flash programming (when V
*2: For Flash programming (when V
*3: When OSC1 crystal oscillator is selected
*4: When OSC3 crystal/ceramic oscillator is selected
( ): Do not mount components if unnecessary.
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
V
DD
V
D1
V
DDQSPI
OSC1
S1C31D50
OSC2
[The potential of the substrate
(back of the chip) is V
OSC3
OSC4
#RESET
TEST
V
SS
is supplied externally)
PP
is generated internally)
PP
Seiko Epson Corporation
23 BASIC EXTERNAL CONNECTION DIAGRAM
SDACOUT_P
External
SDACOUT_N
EXSVDn
External voltage
SENB0
SENA0
REF0
RFIN0
V
DD
REMO
IR transmitter module
Pxy
SDIn
SDOn
SPICLKn
#SPISSn
QSDIO00
.]
SS
QSDIO01
QSDIO02
QSDIO03
QSPICLK0
#QSPISS0
SCLn
SDAn
USINn
USOUTn
TOUTn0/CAPn0
:
TOUTn3/CAPn3
ADIN00–07
#ADTRG0
VREFA0
( )
R
DBG1
SWCLK
SWD
V
PP
circuit
Speaker
R
TMP2
R
TMP1
R
REF
C
REF
I/O
SPI
QSPI
2
I
C
UART
PWM/Capture
A/D conversion inputs
C
VREFA
V
DD
(
)
R
DBG2
Debugging
tool
C
VPP
23-1
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