Qspi Ch.n Interrupt Enable Register; Qspi Ch.n Transmit Buffer Empty Dma Request Enable Register - Epson S1C31D50 Technical Manual

Bit 3 OEIF
Bit 2 TENDIF
Bit 1 RBFIF
Bit 0 TBEIF
These bits indicate the QSPI interrupt cause occurrence status.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag (OEIF, TENDIF)
0 (W): Ineffective
The following shows the correspondence between the bit and interrupt:
QSPI_nINTF.OEIF bit:
QSPI_nINTF.TENDIF bit: End-of-transmission interrupt
QSPI_nINTF.RBFIF bit:
QSPI_nINTF.TBEIF bit:

QSPI Ch.n Interrupt Enable Register

Register name Bit
QSPI_nINTE 15–8 –
7–4 –
3
2
1
0
Bits 15–4 Reserved
Bit 3 OEIE
Bit 2 TENDIE
Bit 1 RBFIE
Bit 0 TBEIE
These bits enable QSPI interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
The following shows the correspondence between the bit and interrupt:
QSPI_nINTE.OEIE bit:
QSPI_nINTE.TENDIE bit: End-of-transmission interrupt
QSPI_nINTE.RBFIE bit:
QSPI_nINTE.TBEIE bit:

QSPI Ch.n Transmit Buffer Empty DMA Request Enable Register

Register name Bit
QSPI_nTBEDMAEN 15–0 TBEDMAEN[15:0]
Bits 15–0 TBEDMAEN[15:0]
These bits enable the QSPI to issue a DMA transfer request to the corresponding DMA channel (Ch.0–
Ch.15) when a transmit buffer empty state has occurred.
1 (R/W): Enable DMA transfer request
0 (R/W): Disable DMA transfer request
Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan-
nels are ineffective.
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Overrun error interrupt
Receive buffer full interrupt
Transmit buffer empty interrupt
Bit name Initial
0x00
0x0
OEIE 0
TENDIE 0
RBFIE 0
TBEIE 0
Overrun error interrupt
Receive buffer full interrupt
Transmit buffer empty interrupt
Bit name Initial
0x0000
Seiko Epson Corporation
15 Quad Synchronous Serial Interface (QSPI)
Reset R/W
– R –
– R
H0 R/W
H0 R/W
H0 R/W
H0 R/W
Reset R/W
H0 R/W –
Remarks
Remarks
15-33