Epson S1C31D50 Technical Manual page 397

Address Register name
0x0020 I2C_0BR
03c4 (I2C Ch.0 Baud-Rate
Register)
0x0020 I2C_0OADR
03c8
(I2C Ch.0 Own
Address Register)
0x0020 I2C_0CTL
03ca
(I2C Ch.0 Control
Register)
0x0020 I2C_0TXD
03cc (I2C Ch.0 Transmit
Data Register)
0x0020 I2C_0RXD
03ce (I2C Ch.0 Receive
Data Register)
0x0020 I2C_0INTF
03d0 (I2C Ch.0 Status
and Interrupt Flag
Register)
0x0020 I2C_0INTE
03d2
(I2C Ch.0 Interrupt
Enable Register)
0x0020 I2C_0TBEDMAEN
03d4
(I2C Ch.0 Transmit
Buffer Empty DMA
Request Enable
Register)
0x0020 I2C_0RBFDMAEN
03d6 (I2C Ch.0 Receive
Buffer Full DMA
Request Enable
Register)
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
APPENDIX A LIST OF PERIPHERAL CIRCUIT CONTROL REGISTERS
Bit Bit name
15–8 –
7 –
6–0 BRT[6:0]
15–10 –
9–0 OADR[9:0]
15–8 –
7–6 –
5 MST
4 TXNACK
3 TXSTOP
2 TXSTART
1 SFTRST
0 MODEN
15–8 –
7–0 TXD[7:0]
15–8 –
7–0 RXD[7:0]
15–13 –
12 SDALOW
11 SCLLOW
10 BSY
9 TR
8 –
7 BYTEENDIF
6 GCIF
5 NACKIF
4 STOPIF
3 STARTIF
2 ERRIF
1 RBFIF
0 TBEIF
15–8 –
7 BYTEENDIE
6 GCIE
5 NACKIE
4 STOPIE
3 STARTIE
2 ERRIE
1 RBFIE
0 TBEIE
15–8 –
7–4 –
3–0 TBEDMAEN[3:0]
15–8 –
7–4 –
3–0 RBFDMAEN[3:0]
Seiko Epson Corporation
Initial Reset R/W
0x00 – R
0 – R
0x7f H0 R/W
0x00 – R
0x000 H0 R/W
0x00 – R
0x0 – R
0 H0 R/W
0 H0/S0 R/W
0 H0/S0 R/W
0 H0/S0 R/W
0 H0 R/W
0 H0 R/W
0x00 – R
0x00 H0 R/W
0x00 – R
0x00 H0 R
0x0 – R
0 H0 R
0 H0 R
0 H0/S0 R
0 H0 R
0 – R
0 H0/S0 R/W
0 H0/S0 R/W
0 H0/S0 R/W
0 H0/S0 R/W
0 H0/S0 R/W
0 H0/S0 R/W
0 H0/S0 R
0 H0/S0 R
0x00 – R
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0x00 – R
0x0 – R
0x0 H0 R/W
0x00 – R
0x0 – R
0x0 H0 R/W
Remarks
–
–
–
–
–
–
Cleared by writing 1.
Cleared by reading the
I2C_0RXD register.
Cleared by writing to the
I2C_0TXD register.
–
–
–
AP-A-33