Data Transfer Control - Epson S1C17001 Technical Manual

20.5 Data Transfer Control

Make the following settings before starting data transfers.
(1) Set the 16-bit timer Ch.2 to output the I
(2) Select the option function. (See section 20.4.)
(3) Set the interrupt conditions to use I
Note: Make sure the I
above settings.
∗ I2CEN: I
2 C Enable Bit in the I
Permitting data transfers
Set the I2CEN (D0/I2C_EN register) to 1 to permit I
input/output.
Note: Do not set I2CEN to 0 when the I
Data transfer start
To start data transfers, the I
sent to establish communications.
(1) Generate start condition
The start condition applies when the SCL line is maintained at High and the SDA line is maintained at Low.
The start condition is generated by setting STRT (D0/I2C_CTL register) to 1.
∗ STRT: Start Control Bit in the I
STRT is automatically reset to 0 once the start condition is generated.
(2) Slave address transmission
Once the start condition has been generated, the I
dress and transfer direction for communications. I
an 8-bit transfer data register to send the slave address and transfer direction bit, enabling single transfers in
7-bit address mode. In 10-bit mode, data is sent twice under software control. Figure 20.5.2 gives the configu-
ration of the address data.
7-bit address
10-bit address
First data sent
Second data sent
Figure 20.5.2: Slave address and transmission data specifying transfer direction
S1C17001 TECHNICAL MANUAL
2 C clock. (See Section 11.)
2 C interrupts. (See Section 20.6.)
2 C module is halted (when I2CEN/I2C_EN register = 0) before changing the
2 C Enable (I2C_EN) Register (D0/0x4340)
2
C module is transferring data.
2 C master (this module) must generate the start condition. The slave address is then
SDA (output)
SCL (output)
Start condition
Figure 20.5.1: Start condition
2
C Control (I2C_CTL) Register (D0/0x4342)
D7 D6 D5 D4
A6 A5 A4 A3
Slave address
D7 D6 D5 D4
1 1 1 1
D7 D6 D5 D4
A7 A6 A5 A4
Slave address last 8 bits
C operations. This enables I
2
C master (this module) sends a bit indicating the slave ad-
2
2 C slave addresses are either 7-bit or 10-bit. This module uses
D3 D2 D1 D0
A2 A1 A0 DIR
Transfer direction
0: Master → Slave (data transmission)
1: Slave → Master (date receipt)
D3 D2 D1 D0
0 A9 A8 DIR
Transfer direction
Slave address
0: Master → Slave (data transmission)
first 2 bits
1: Slave → Master (date receipt)
D3 D2 D1 D0
A3 A2 A1 A0
EPSON
20 I
C transfers and permits clock
2
2
C
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