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17.3 Watchdog Timer Control
17.3.1 NMI/Reset Mode Selection
WDTMD (D1/WDT_ST register) is used to select whether an NMI signal or a reset signal is output when the
watchdog timer has not been reset within the NMI/Reset occurrence cycle.
∗ WDTMD: NMI/Reset Mode Select Bit in the Watchdog Timer Status (WDT_ST) Register (D1/0x5041)
To generate an NMI, set WDTMD to 0 (default). Set to 1 to generate a reset.
17.3.2 Watchdog Timer Run/Stop Control
The watchdog timer starts counting when a value other than 0b1010 is written to WDTRUN[3:0] (D[3:0]/
WDT_CTL register) and stops when 0b1010 is written.
∗ WDTRUN[3:0]: Watchdog Timer Run/Stop Control Bits in the Watchdog Timer Control (WDT_CTL) Register
(D[3:0]/0x5040)
Initial resetting sets WDTRUN[3:0] to 0b1010 and stops the watchdog timer.
Since an NMI or Reset may be generated immediately after running depending on the counter value, the watchdog
timer should also be reset concurrently (before running the watchdog timer), as explained in the following section.
17.3.3 Watchdog Timer Resetting
To reset the watchdog timer, write 1 to WDTRST (D4/WDT_CTL register).
∗ WDTRST: Watchdog Timer Reset Bit in the Watchdog Timer Control (WDT_CTL) Register (D4/0x5040)
A location should be provided for periodically processing the routine for resetting the watchdog timer before an
NMI or Reset is generated when using the watchdog timer. Process this routine within 131,072/f
onds when f
= 32.768 kHz) cycle.
OSC1
After resetting, the watchdog timer starts counting with a new NMI/Reset generation cycle.
If the watchdog timer is not reset within the NMI/Reset generation cycle for any reason, the CPU is switched to
interrupt processing by NMI or resetting, an interrupt vector is read out, and an interrupt processing routine is ex-
ecuted.
The reset and NMI vector addresses are 0x8000 and 0x8008.
If the counter overflows and generates an NMI without the watchdog timer being reset, WDTST (D0/WDT_ST
register) is set to 1.
∗ WDTST: NMI Status Bit in the Watchdog Timer Status (WDT_ST) Register (D0/0x5041)
This bit is provided to confirm that the watchdog timer was the source of the NMI.
The WDTST set to 1 is cleared to 0 by resetting the watchdog timer.
17.3.4 Operation in Standby Mode
HALT mode
The watchdog timer operates in HALT mode, as the clock is fed. HALT mode is therefore canceled by an NMI
or Reset if it continues for more than the NMI/Reset cycle. To disable the watchdog timer while in HALT
mode, stop the watchdog timer by writing 0b1010 to WDTRUN[3:0] before executing the halt command. Reset
the watchdog timer before resuming operations after HALT mode is canceled.
SLEEP mode
The clock fed from the OSC module is stopped in SLEEP mode, which also stops the watchdog timer. To pre-
vent generation of an unnecessary NMI or Reset after canceling SLEEP mode, reset the watchdog timer before
executing the slp command. The watchdog should also be stopped as required using WDTRUN[3:0].
S1C17001 TECHNICAL MANUAL
EPSON
17 WATCHDOG TIMER (WDT)
second (4 sec-
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205
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