Precautions - Epson S1C17001 Technical Manual

Cmos 16-bit single chip microcontroller
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10 INPUT/OUTPUT PORT (P)

10.9 Precautions

Operation clock
• The PCLK clock must be fed from the clock generator to access the input/output port.
The prescaler output clock is also needed to operate the P0 port chattering filter. Switch on the prescaler
when using this function.
Pull-up
• A delay will occur in the waveform rise-up depending on time constants such as pull-up resistance and pin
load capacitance if the port pin is switched from Low level to High level by the internal pull-up resistor. An
appropriate wait time must be set for the input/output port loading. The wait time set should be a value not
less than that calculated from the following equation.
Wait time = R
x (C
IN
R
: pull-up resistance maximum value
IN
C
: pin capacitance maximum value
IN
• Input/output ports that are not used should be set with pull-up resistance enabled.
P0 and P1 port interrupts
• To prevent generating unnecessary interrupts, reset the corresponding interrupt flag—P0IF[7:0] (0x5207) or
P1IF[7:0] (0x5217)—before permitting interrupts for the required port with the P0_IMSK register (0x5205)
or P1_IMSK register (0x5215).
• Set the ITC P0 and P1 port interrupt trigger mode to level trigger mode.
Reset the P port module interrupt flag P0IF[7:0] (0x5207) and P1IF[7:0] (0x5217) within the interrupt pro-
cessing routine after the interrupt occurs. This also resets the ITC interrupt flag.
P0 Port chattering filter circuit
• Input interrupts will not be accepted for a transition into SLEEP mode with the chattering filter left on. The
chattering filter should be set off (no verification time) before executing the slp command.
• P0 port interrupts must be blocked when P0_CHAT register (0x5208) settings are being changed. Changing
the setting while interrupts are permitted may generate inadvertent P0 interrupts.
• The chattering filter verification time refers to the maximum pulse width that can be filtered. Generating an
input interrupt requires a minimum input time of the verification time and a maximum input time of twice the
verification time.
• A phenomenon may occur in which the internal signal oscillates due to the time elapsed until the signal
reaches the threshold value if the input signal rise-up/drop-off time is delayed. Since input interrupts will
malfunction under these conditions, the input signal rise-up/drop-off time should normally be set to 25 ns or
less.
P0 port key-entry reset
• Make sure the specified ports are not simultaneously switched to Low during normal operations when using
the P0 port key-entry reset function.
• The P0 port key entry reset function is disabled on initial resetting and cannot be used for resetting at power-
on.
• The P0 port key-entry reset function cannot be used in SLEEP state.
106
+ load capacitance on board) x 1.6 [s]
IN
EPSON
S1C17001 TECHNICAL MANUAL

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