Epson S1C17001 Technical Manual page 339

APPENDIX B POWER SAVING
This section describes clock systems that can be controlled via software and power-saving control details. For more
information on control registers and control methods, refer to the respective module sections.
System SLEEP (All clocks stopped)
• Execute slp command
Execute the slp command when the entire system can be stopped. The CPU switches to SLEEP mode and
the system clocks stop. This also stops all peripheral circuits using clocks. Starting up the CPU from SLEEP
mode is therefore limited to startup using ports (described later).
System clocks
• Clock source selection (OSC module)
Select between OSC3 and OSC1 for the system clock source. Reduce current consumption by selecting the
OSC1 clock when low-speed processing is possible.
• OSC3 oscillation circuit stop (OSC module)
Operate the oscillation circuit comprising the system clock source. Where possible, stop the other circuit.
You can reduce current consumption by using OSC1 as the system clock and stopping the OSC3 oscillation
circuit.
CPU clock (CCLK)
• Execute the halt command
Execute the halt command when program execution by the CPU is not required—for example, when only
the display is required or for interrupt standby. The CPU switches to HALT mode and suspends operations,
but the peripheral circuits maintain the status in place at the time of the halt command, enabling use of pe-
ripheral circuits for timers and interrupts. You can reduce power consumption even further by suspending un-
necessary peripheral circuits before executing the halt command. The CPU is started from HALT mode using
the port or interrupts from the peripheral circuit operating in HALT mode.
• Low-speed clock gear selection (CLG module)
The CLG module can reduce CPU clock speeds to between 1/1 and 1/8 of the system clock via the clock gear
settings. Reduce current consumption by operating the CPU at the minimum speed required for applications.
Peripheral clock (PCLK)
• PCLK stop (CLG module)
Stop the PCLK clock feed from the CLG to peripheral circuits if none of the following peripheral circuits is
required.
Peripheral circuits operating with PCLK
• Prescaler (PWM & capture timer, remote controller, P port)
• UART
• 8-bit timer
• 16-bit timer Ch.0 to Ch.2
• Interrupt controller
• SPI
• I 2 C
• P port and port MUX (control register, chattering filter)
• PWM & capture timer
• MISC register
• Remote controller
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S1C17001 TECHNICAL MANUAL