0X4206: 8-Bit Timer Control Register (T8F_Ctl) - Epson S1C17001 Technical Manual

12 8-BIT TIMER (T8F)

0x4206: 8-bit Timer Control Register (T8F_CTL)

Register name Address Bit
8-bit Timer 0x4206 D15–12 –
Control Register (16 bits)
D11–8 TFMD[3:0] Fine mode setup
(T8F_CTL)
D7–5 –
D4
D3–2 –
D1
D0
D[15:12] Reserved
D[11:8] TFMD[3:0]: Fine Mode Setup Bits
Correct the transfer rate error. (Default: 0x0)
The TFMD[3:0] bit specifies the delay pattern to be inserted into the 16 underflow intervals. Inserting
one delay extends the output clock cycle by one count clock cycle. This setting delays the interrupt tim-
ing in the same way.
TFMD[3:0]
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xa
0xb
0xc
0xd
0xe
0xf
Underflow signal (no correction)
Underflow signal (with correction)
Output clock (no correction)
Output clock (with correction)
D[7:5] Reserved
138
Name Function
reserved
reserved
TRMD Count mode select
reserved
PRESER Timer reset
PRUN Timer run/stop control
Table 12.10.3: Delay patterns specified by TFMD[3:0]
1 2 3 4 5
– – – – –
– – – – –
– – – – –
– – – – –
– – – D –
– – – D –
– – – D –
– – – D –
– D – D –
– D – D –
– D – D –
– D – D –
– D D D –
– D D D –
– D D D D
– D D D D
Count clock
15
15
Figure 12.10.1: Delay cycle insertion in Fine mode
Setting
–
0x0 to 0xf
–
1 One shot 0 Repeat
–
1 Reset 0 Ignored
1 Run 0 Stop
Underflow number
6 7 8 9 10
– – – – –
– – – – –
– – D – –
– – D – –
– – D – –
– – D – –
D – D – –
D – D – D
D – D – D
D – D – D
D D D – D
D D D – D
D D D – D
D D D – D
D D D – D
D D D D D
D: Indicates the insertion of a delay cycle.
16
16
EPSON
Init. R/W Remarks
– – 0 when being read.
0x0 R/W Set a number of times
to insert delay into a
16-underflow period.
– – 0 when being read.
0 R/W
– – 0 when being read.
0 W
0 R/W
11 12 13 14 15
– – – –
– – – –
– – – –
– D – –
– D – –
– D – D
– D – D
– D – D
– D – D
– D – D
– D – D
D D – D
D D – D
D D D D
D D D D
D D D D
1
Delay
S1C17001 TECHNICAL MANUAL
16
– –
– D
– D
– D
– D
– D
– D
– D
– D
D D
D D
D D
D D
D D
D D
D D
1