16-Bit Timer Interrupts - Epson S1C17001 Technical Manual

11 16-BIT TIMER (T16)

11.8 16-bit Timer Interrupts

The 16-bit timer outputs interrupt requests to the interrupt controller (ITC) when the counter underflows.
To generate a timer underflow interrupt, the interrupt level and interrupt permission should be set using the ITC
registers.
Timer interrupt ITC registers
Table 11.8.1 lists the ITC control registers for each timer channel.
Timer channel
Ch.0
Ch.1
Ch.2
ITC_IFLG register (0x4300)
ITC_EN register (0x4302)
ITC_ILV0 register (0x430e)
ITC_ILV1 register (0x4310)
If an underflow occurs in the timer, the corresponding interrupt flag is set to 1.
If the interrupt enable bit corresponding to that interrupt flag is set to 1, the ITC sends an interrupt request to
the S1C17 core. To prohibit timer interrupts, set the interrupt enable bit to 0 beforehand. The interrupt flag will
be set to 1 by the timer underflow pulse regardless of the interrupt enable bit setting (i.e., even if set to 0).
The interrupt level setting bit sets the timer interrupt level (0 to 7). If set to the same interrupt level, the 16-bit
timer Ch.0 takes the highest priority, while the 16-bit timer Ch.2 takes the lowest priority.
The S1C17 core accepts interrupts when all of the following conditions are satisfied:
• The interrupt enable bit has been set to 1.
• The PSR (S1C17 core internal processor status register) IE (interrupt enable) bit has been set to 1.
• The timer interrupt has a higher interrupt level set than that set for the PSR IL (interrupt level).
• No other interrupt factors having higher precedence (e.g., NMI) are present.
For more information on these interrupt control registers and operations when interrupts occur, see "6 Interrupt
Controller (ITC)."
Interrupt vectors
The timer interrupt vector numbers and vector addresses are listed below.
116
Table 11.8.1: ITC registers
Interrupt flag
IIFT1 (D9/ITC_IFLG)
IIFT2 (D10/ITC_IFLG)
IIFT3 (D11/ITC_IFLG)
Table 11.8.2: Timer interrupt vectors
Timer channel Vector number
Timer Ch.0
Timer Ch.1
Timer Ch.2
Interrupt enable bit
IIEN1 (D9/ITC_EN)
IIEN2 (D10/ITC_EN)
IIEN3 (D11/ITC_EN)
Vector address
13 (0x0d) 0x8034
14 (0x0e) 0x8038
15 (0x0f) 0x803c
EPSON
Interrupt level setting bit
IILV1[2:0] (D[10:8]/ITC_ILV0)
IILV2[2:0] (D[2:0]/ITC_ILV1)
IILV3[2:0] (D[10:8]/ITC_ILV1)
S1C17001 TECHNICAL MANUAL