Processing For Multiple Interrupts - Epson S1C17001 Technical Manual

6.3.4 Processing for Multiple Interrupts

The ITC ITC_ELVx and ITC_ILVx registers (0x4306 to 0x4314) set the interrupt levels (0 to 7) for the various in-
terrupt factors.
Vector No. Hardware interrupt
4 P0 port interrupt
5 P1 port interrupt
6 Stopwatch timer interrupt
7 Clock timer interrupt
8 8-bit OSC1 timer interrupt
11 PWM & capture timer interrupt
12 8-bit timer interrupt
13 16-bit timer Ch.0 interrupt
14 16-bit timer Ch.1 interrupt
15 16-bit timer Ch.2 interrupt
16 UART interrupt
17 Remote controller interrupt
18 SPI interrupt
19 I 2 C interrupt
The interrupt level can range from 0 to 7.
The interrupt level set is issued to the S1C17 core at the same time as an interrupt request from the ITC. This inter-
rupt level is used in the S1C17 core to prohibit subsequent interrupts with the same or lower levels (refer to Section
6.3.6).
Initial resets reset all interrupt levels to 0. The S1C17 core rejects interrupt requests if the interrupt level is 0.
The ITC uses the interrupt level when multiple interrupt factors occur simultaneously.
If multiple interrupts occur at the same time permitted by the interrupt enable bit, the ITC sends the interrupt re-
quest with the highest level set by the ITC_ELVx and ITC_ILVx registers to the S1C17 core.
If multiple interrupt factors with the same interrupt level occur simultaneously, the interrupt with the lowest vector
number is processed first. The other interrupts are held until all have been accepted by the S1C17 core in descend-
ing order of priority.
If an interrupt factor of higher priority occurs while the ITC outputs an interrupt request signal to the S1C17 core
(before acceptance by the S1C17 core), the ITC alters the vector number and interrupt level signal to the setting de-
tails of the most recent interrupt. The immediately preceding interrupt is held.
S1C17001 TECHNICAL MANUAL
Table 6.3.4.1: Interrupt level setting bits
Interrupt level setting bit
EILV0[2:0] (D[2:0]/ITC_ELV0 register)
EILV1[2:0] (D[10:8]/ITC_ELV0 register)
EILV2[2:0] (D[2:0]/ITC_ELV1 register)
EILV3[2:0] (D[10:8]/ITC_ELV1 register)
EILV4[2:0] (D[2:0]/ITC_ELV2 register)
EILV7[2:0] (D[10:8]/ITC_ELV3 register)
IILV0[2:0] (D[2:0]/ITC_ILV0 register)
IILV1[2:0] (D[10:8]/ITC_ILV0 register)
IILV2[2:0] (D[2:0]/ITC_ILV1 register)
IILV3[2:0] (D[10:8]/ITC_ILV1 register)
IILV4[2:0] (D[2:0]/ITC_ILV2 register)
IILV5[2:0] (D[10:8]/ITC_ILV2 register)
IILV6[2:0] (D[2:0]/ITC_ILV3 register)
IILV7[2:0] (D[10:8]/ITC_ILV3 register)
EPSON
6 INITERRUPT CONTROLLER
Register address
0x4306
0x4306
0x4308
0x4308
0x430a
0x430c
0x430e
0x430e
0x4310
0x4310
0x4312
0x4312
0x4314
0x4314
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