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0x5207/5217: Px Port Interrupt Flag Registers (Px_IFLG)
Register name Address
Bit
P0 Port
0x5207
D7–0 P0IF[7:0]
Interrupt Flag
(8 bits)
Register
(P0_IFLG)
P1 Port
0x5217
D7–0 P1IF[7:0]
Interrupt Flag
(8 bits)
Register
(P1_IFLG)
Note: The "x" in the bit names indicates the port number (0 or 1).
D[7:0]
PxIF[7:0]: Px[7:0] Port Interrupt Flags
These are interrupt flags indicating the interrupt factor occurrence status.
1(R):
Interrupt factor present
0(R):
No interrupt factor (default)
1(W):
Reset flag
0(W):
Disabled
PxIF[7:0] are interrupt flags corresponding to the individual 16 ports of P0[7:0] and P1[7:0]. Setting
the corresponding PxIE[7:0] (Px_IMSK register) to 1 sets PxIF[7:0] to 1 at the specified edge (rising or
falling edge) of the input signal. A P0 or P1 port interrupt request signal is also output to the ITC at the
same time. This interrupt request signal causes the P0/P1 port interrupt flag inside the ITC to be set to 1.
Meeting the ITC and S1C17 core interrupt conditions generates an interrupt.
The following processing is needed to manage the interrupt factor occurrence state using the PxIF[7:0].
1. Set the ITC P0 and P1 interrupt trigger mode to level trigger mode.
2. Reset the P port module interrupt flag PxIF[7:0] within the interrupt processing routine after the
interrupt occurs (this also resets the ITC interrupt flag).
PxIF[7:0] is reset by writing as 1.
Note: To prevent genarating unnecessary interrupts, reset the relevant PxIF[7:0] before
permitting interrupts for the required port using PxIE[7:0] (Px_IMSK register).
∗ P0IE[7:0]: P0[7:0] Port Interrupt Enable Bits in the P0 Port Interrupt Mask (P0_IMSK) Register
∗ P1IE[7:0]: P1[7:0] Port Interrupt Enable Bits in the P1 Port Interrupt Mask (P1_IMSK) Register
S1C17001 TECHNICAL MANUAL
Name
Function
P0[7:0] port interrupt flag
P1[7:0] port interrupt flag
(D[7:0]/0x5205)
(D[7:0]/0x5215)
Setting
1 Cause of
0 Cause of
interrupt
occurred
1 Cause of
0 Cause of
interrupt
occurred
EPSON
10 INPUT/OUTPUT PORT (P)
Init. R/W
Remarks
0
R/W Reset by writing 1.
interrupt not
occurred
0
R/W Reset by writing 1.
interrupt not
occurred
99
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