16-Bit Timer Operating Modes; Internal Clock Mode - Epson S1C17001 Technical Manual

11 16-BIT TIMER (T16)

11.2 16-bit Timer Operating Modes

The 16-bit timer has the following three operating modes:
1. Internal clock mode (Normal timer counting internal clock)
2. External clock mode (Functions as event counter)
3. Pulse width measurement mode (Counts external input pulse width using internal clock)
The operating mode is selected using CKSL[1:0] (D[9:8]/T16_CTLx register).
∗ CKSL[1:0]: Input Clock and Pulse Width Count Mode Select Bits in the 16-bit Timer Ch.x Control (T16_CTLx)
Register (D[9:8]/0x4226/0x4246/0x4266)

11.2.1 Internal Clock Mode

Internal clock mode uses the prescaler output clock as the count clock.
The timer counts down from the initial value set in the reload data register and outputs an underflow signal when
the counter underflows. The underflow signal is used to generate an interrupt and an internal serial interface clock.
The time until underflow occurs can be finely programmed by selecting the prescaler clock and initial counter
value, making it useful for serial transfer clock generation and sporadic time measurement.
Count clock selection
The count clock is selected by the DF[3:0] (D[3:0]/T16_CLKx register) from the 15 types generated by the pr-
escaler dividing the PCLK clock into 1/1 to 1/16 K divisions.
∗ DF[3:0]: Timer Input Clock Select Bits in the 16-bit Timer Ch.x Input Clock Select (T16_CLKx) Register
(D[3:0]/0x4220/0x4240/0x4260)
DF[3:0]
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
Note: • The prescaler must run before operating the 16-bit timer in internal clock mode.
• Make sure the 16-bit timer count is halted before changing count clock settings.
For detailed information on the prescaler control, see "9 Prescaler (PSC)."
108
Table 11.2.1: Operating mode selection
CKSL[1:0]
0x3
0x2 Pulse width measurement mode
0x1
0x0
Table 11.2.1.1: Count clock selection
Prescaler output clock
Reserved
PCLK-1/16384
PCLK-1/8192
PCLK-1/4096
PCLK-1/2048
PCLK-1/1024
PCLK-1/512
PCLK-1/256
EPSON
Operating mode
Reserved
External clock mode
Internal clock mode
(Default: 0x0)
DF[3:0] Prescaler output clock
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
PCLK-1/128
PCLK-1/64
PCLK-1/32
PCLK-1/16
PCLK-1/8
PCLK-1/4
PCLK-1/2
PCLK-1/1
(Default: 0x0)
S1C17001 TECHNICAL MANUAL