Clock Supply In Debug Mode; Operations; Svd3 Control - Epson Arm S1C31 Series Technical Manual

11.3.3 Clock Supply in DEBUG Mode

The CLK_SVD3 supply during DEBUG mode should be controlled using the SVD3CLK.DBRUN bit.
The CLK_SVD3 supply to SVD3 is suspended when the CPU enters DEBUG mode if the SVD3CLK.DBRUN bit
= 0. After the CPU returns to normal mode, the CLK_SVD3 supply resumes. Although SVD3 stops operating when
the CLK_SVD3 supply is suspended, the registers retain the status before DEBUG mode was entered.
If the SVD3CLK.DBRUN bit = 1, the CLK_SVD3 supply is not suspended and SVD3 will keep operating in DE-
BUG mode.

11.4 Operations

11.4.1 SVD3 Control

Starting detection
SVD3 should be initialized and activated with the procedure listed below.
1. Write 0x0096 to the SYSPROT.PROT[15:0] bits. (Remove system protection)
2. Configure the operating clock using the SVD3CLK.CLKSRC[1:0] and SVD3CLK.CLKDIV[2:0] bits.
3. Set the following SVD3CTL register bits:
- SVD3CTL.VDSEL and SVD3CTL.EXSEL bits (Select detection voltage (V
- SVD3CTL.SVDSC[1:0] bits
- SVD3CTL.SVDC[4:0] bits
- SVD3CTL.SVDRE[3:0] bits
- SVD3CTL.SVDMD[1:0] bits
4. Set the following bits when using the interrupt:
- Write 1 to the SVD3INTF.SVDIF bit.
- Set the SVD3INTE.SVDIE bit to 1.
5. Set the SVD3CTL.MODEN bit to 1.
6. Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits.
Terminating detection
Follow the procedure shown below to stop SVD3 operation.
1. Write 0x0096 to the SYSPROT.PROT[15:0] bits. (Remove system protection)
2. Write 0 to the SVD3CTL.MODEN bit.
3. Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits.
Reading detection results
The following two detection results can be obtained by reading the SVD3INTF.SVDDT bit:
• When SVD3INTF.SVDDT bit = 0
Power supply voltage (V
• When SVD3INTF.SVDDT bit = 1
Power supply voltage (V
Before reading the SVD3INTF.SVDDT bit, wait for at least SVD circuit enable response time after 1 is written
to the SVD3CTL.MODEN bit (refer to "Supply Voltage Detector Characteristics, SVD circuit enable response
time t " in the "Electrical Characteristics" chapter).
SVDEN
After the SVD3CTL.SVDC[4:0] bits setting value is altered to change the SVD detection voltage V
VD detection voltage V
time before reading the SVD3INTF.SVDDT bit (refer to "Supply Voltage Detector Characteristics, SVD circuit
response time t " in the "Electrical Characteristics" chapter).
SVD
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
, EXSVDn) ≥ SVD detection voltage V
DD
, EXSVDn) < SVD detection voltage V
DD
when the SVD3CTL.MODEN bit = 1, wait for at least SVD circuit response
SVD_EXT
Seiko Epson Corporation
11 SUPPLY VOLTAGE DETECTOR (SVD3)
(Set low power supply voltage detection counter)
(Set SVD detection voltage V
voltage V )
SVD_EXT
(Select reset/interrupt mode)
(Set intermittent operation mode)
(Clear interrupt flag)
(Enable SVD3 interrupt)
(Enable SVD3 detection)
(Set system protection)
(Disable SVD3 detection)
(Set system protection)
or EXSVD detection voltage V
SVD
or EXSVD detection voltage V
SVD
, EXSVD0, or EXSVD1))
DD
/EXSVD detection
SVD
SVD_EXT
SVD_EXT
/EXS-
SVD
11-3