Epson Arm S1C31 Series Technical Manual page 190

Cmos 32-bit single chip microcontroller
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If transmit data has not been written to the QSPI_nTXD register after the last clock is output from the QSPI-
CLKn pin, the clock output halts and the QSPI_nINTF.TENDIF bit is set to 1. At the same time QSPI issues an
end-of-transmission interrupt request if the QSPI_nINTE.TENDIE bit = 1.
QSPICLKn
QSDIOn[3:0]
QSPI_nINTF.TBEIF
QSPI_nINTF.TENDIF
Software operations
Figure 15.5.4.1 Example of Data Sending Operations in Master Mode
(QSPI_nMOD.CHDL[3:0] bits = QSPI_nMOD.CHLN[3:0] bits = 0x3)
Set the transfer direction to output
(
Assert the slave select signal output from
the #QSPISSn pin (QSPI_nCTL.MSTSSO
Read the QSPI_nINTF.TBEIF bit
(
Negate the slave select signal output from
the #QSPISSn pin (QSPI_nCTL.MSTSSO
Data transmission using DMA
By setting the QSPI_nTBEDMAEN.TBEDMAENx bit to 1 (DMA transfer request enabled), a DMA transfer
request is sent to the DMA controller and transmit data is transferred from the specified memory to the QSPI_
nTXD register via DMA Ch.x when the QSPI_nINTF.TBEIF bit is set to 1 (transmit buffer empty).
This automates the procedure from Step 3 to Step 6 described above.
The transfer source/destination and control data must be set for the DMA controller and the relevant DMA
channel must be enabled to start a DMA transfer in advance so that transmit data will be transferred to the
QSPI_nTXD register. For more information on DMA, refer to the "DMA Controller" chapter.
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
1
2
3
4
Data (W) → QSPI_nTXD
Data (W) → QSPI_nTXD
Data transmission
(QSPI_nCTL.DIR = 0)
= 0) or a general-purpose port
QSPI_nINTF.TBEIF = 1 ?
YES
Write transmit data to
the QSPI_nTXD register
Transmit data remained?
NO
= 1) or a general-purpose port
End
Figure 15.5.4.2 Data Transmission Flowchart in Master Mode
Seiko Epson Corporation
15 Quad Synchronous Serial Interface (QSPI)
1
2
3
4
Not necessary
in single transfer mode
)
NO
YES
Wait for an interrupt request
(QSPI_nINTF.TBEIF = 1)
)
1
2
3
4
Data (W) → QSPI_nTXD
1 (W) → QSPI_nINTF.TENDIF
15-13

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