Epson Arm S1C31 Series Technical Manual page 37

2 POWER SUPPLY, RESET, AND CLOCKS
(1) When the CLGOSC.OSC1SLPC bit = 1
SYSCLK
(CPU operating clock)
Real-time clock
operating clock
(2) When the CLGOSC.OSC1SLPC bit = 0
SYSCLK
(CPU operating clock)
Real-time clock
operating clock
The SYSCLK condition (clock source and division ratio) at wake-up from SLEEP mode to RUN mode can also
be configured. This allows flexible clock control according to the wake-up process. Configure the clock using
the CLGSCLK.WUPSRC[1:0] and CLGSCLK.WUPDIV[1:0] bits, and write 1 to the CLGSCLK.WUPMD bit
to enable this function.
(1) When the CLGSCLK.WUPMD bit = 0
SYSCLK
(CPU operating clock)
CLGSCLK.CLKSRC[1:0] = 0x1 (OSC1)
CLGSCLK.WUPSRC[1:0] = 0x1 (OSC1)
(2) When the CLGSCLK.WUPMD bit = 1 and the CLGSCLK.WUPSRC[1:0] bits = 0x0
SYSCLK
(CPU operating clock)
CLGSCLK.CLKSRC[1:0] = 0x1 (OSC1)
CLGSCLK.WUPSRC[1:0] = 0x0 (IOSC)
Clock external output (FOUT)
The FOUT pin can output the clock generated by a clock source or its divided clock to outside the IC. This al-
lows monitoring the oscillation frequency of the oscillator circuit or supplying an operating clock to external
ICs. Follow the procedure shown below to start clock external output.
1. Assign the FOUT function to the port.
2. Configure the following CLGFOUT register bits:
- CLGFOUT.FOUTSRC[1:0] bits
- CLGFOUT.FOUTDIV[2:0] bits
- Set the CLGFOUT.FOUTEN bit to 1. (Enable clock external output)
OSC3 oscillation auto-trimming function
The auto-trimming function adjusts the OSC3CLK clock frequency by trimming the clock with reference to
the high precision OSC1CLK clock generated by the OSC1 oscillator circuit (crystal oscillator). However, this
function is effective only when 16 MHz (CLGOSC3.OSC3FQ[1:0] bits = 0x3) has been selected to the OSC3
oscillation frequency.
2-12
IOSCCLK
(CPU stop, CLK stop)
Executing the WFI/WFE instruction
(SLEEPDEEP bit = 1)
OSC1CLK
∗ The real-time clock is turned off in
SLEEP mode as the clock stops.
IOSCCLK
(CPU stop, CLK stop)
Executing the WFI/WFE instruction
(SLEEPDEEP bit = 1)
∗ The real-time clock keeps operating in
SLEEP mode as the clock is being supplied.
Figure 2.3.4.3 Clock Control Example in SLEEP Mode
OSC1CLK
(CPU stop, CLK stop)
Executing the WFI/WFE instruction
(SLEEPDEEP bit = 1)
OSC1CLK
(CPU stop, CLK stop)
Executing the WFI/WFE instruction
(SLEEPDEEP bit = 1)
Figure 2.3.4.4 Clock Control Example at SLEEP Cancelation
(Refer to the "I/O Ports" chapter.)
(Select clock source)
(Set clock division ratio)
Seiko Epson Corporation
Oscillation stabilization waiting time
SLEEP mode IOSCCLK
(Unstable)
Interrupt
(Wake-up)
OSC1CLK
(CLK stop)
(Unstable)
SLEEP mode
IOSCCLK
(Unstable)
Interrupt
(Wake-up)
OSC1CLK
Oscillation stabilization waiting time
SLEEP mode OSC1CLK
(Unstable)
Interrupt
(Wake-up)
∗ Starting up with the same clock as one
that used before SLEEP mode was entered.
SLEEP mode IOSCCLK
(Unstable)
Interrupt
(Wake-up)
CLGSCLK.CLKSRC[1:0] = 0x0 (IOSC)
CLGSCLK.WUPSRC[1:0] = 0x0 (IOSC)
∗ Switching to IOSC that features fast
initiation allows high-speed processing.
IOSCCLK
OSC1CLK
IOSCCLK
OSC1CLK
IOSCCLK
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)