Clock Supply During Debugging; Spi Clock (Spiclkn) Phase And Polarity - Epson Arm S1C31 Series Technical Manual

14 SYNCHRONOUS SERIAL INTERFACE (SPIA)
f
f = — — — — — — — — —
SPICLK
2 × (RLD + 1)
Where
f :
SPICLK
f : SPIA operating clock frequency [Hz]
CLK_SPIA
RLD:
For controlling the 16-bit timer, refer to the "16-bit Timers" chapter.
Operating clock in slave mode
SPIA set in slave mode operates with the clock supplied from the external SPI master to the SPICLKn pin. The
16-bit timer channel (including the clock source selector and the divider) corresponding to the SPIA channel is
not used. Furthermore, the SPIA_nMOD.NOCLKDIV bit setting becomes ineffective.
SPIA keeps operating using the clock supplied from the external SPI master even if all the internal clocks halt
during SLEEP mode, so SPIA can receive data and can generate receive buffer full interrupts.

14.3.2 Clock Supply During Debugging

In master mode, the operating clock supply during debugging should be controlled using the T16_mCLK.DBRUN
bit.
The CLK_T16_m supply to SPIA Ch.n is suspended when the CPU enters debug state if the T16_mCLK.DBRUN
bit = 0. After the CPU returns to normal operation, the CLK_T16_m supply resumes. Although SPIA Ch.n stops
operating when the CLK_T16_m supply is suspended, the output pins and registers retain the status before the de-
bug state was entered. If the T16_mCLK.DBRUN bit = 1, the CLK_T16_m supply is not suspended and SPIA Ch.n
will keep operating in a debug state.
SPIA in slave mode operates with the external SPI master clock input from the SPICLKn pin regardless of whether
the CPU is placed into debug state or normal operation state.
14.3.3 SPI Clock (SPICLK n ) Phase and Polarity
The SPICLKn phase and polarity can be configured separately using the SPIA_nMOD.CPHA bit and the SPIA_
nMOD.CPOL bit, respectively. Figure 14.3.3.1 shows the clock waveform and data input/output timing in each set-
ting.
SPIA_nMOD register
CPOL bit CPHA bit
1 1
1 0
0 1
0 0
x x
x x
(Master mode)
x 1
(Slave mode)
x 0
(Slave mode)
Figure 14.3.3.1 SPI Clock Phase and Polarity (SPIA_nMOD.LSBFST bit = 0, SPIA_nMOD.CHLN[3:0] bits = 0x7)
14-4
CLK_SPIA
SPICLKn frequency [Hz] (= baud rate [bps])
16-bit timer reload data value
Cycle No. 1
SPICLKn
SPICLKn
SPICLKn
SPICLKn
SDIn MSB
SDOn MSB
SDOn MSB
SDOn
MSB
Writing data to the SPIA_nTXD register
Seiko Epson Corporation
f
CLK_SPIA
RLD = — — — — — — — - 1
f
SPICLK
2 3 4
(Eq. 14.1)
× 2
5 6 7
LSB
LSB
LSB
LSB
S1C31D41 TECHNICAL MANUAL
8
(Rev. 1.1)