Common Registers Between Port Groups - Epson Arm S1C31 Series Technical Manual

7 I/O PORTS (PPORT)
Register name Bit
PDRCTL 15–12 –
(Pd Port Pull-up/down
11
Control Register)
10
9
8
7–4 –
3
2
1
0
PDMODSEL 15–8 –
(Pd Port Mode Select
7–4 –
Register)
3
2
1
0
PDFNCSEL 15–8 –
(Pd Port Function
7–6 PD3MUX[1:0]
Select Register)
5–4 PD2MUX[1:0]
3–2 PD1MUX[1:0]
1–0 PD0MUX[1:0]
PDSELy = 0
Port
PDyMUX = 0x0
name GPIO
(Function 0)
Peripheral
Pd0 Pd0
CPU
Pd1 Pd1
CPU
Pd2 Pd2 –
Pd3 Pd3 –

7.7.9 Common Registers between Port Groups

Table 7.7.9.1 Control Registers for Common Use with Port Groups
Register name Bit
PPORTCLK 15–9 –
(P Port Clock Control
8
Register)
7–4 CLKDIV[3:0]
3–2 –
1–0 CLKSRC[1:0]
PPORTINTFGRP 15–8 –
(P Port Interrupt Flag
7
Group Register)
6
5
4
3
2
1
0
7-28
Bit name Initial
0x0
PDPDPU3 0
PDPDPU2 0
PDPDPU1 0
PDPDPU0 0
0x0
PDREN3 0
PDREN2 0
PDREN1 0
PDREN0 0
0x00
0x0
PDSEL3 0
PDSEL2 0
PDSEL1 1
PDSEL0 1
0x00
0x0
0x0
0x0
0x0
Table 7.7.8.2 Pd Port Group Function Assignment
PDyMUX = 0x1
(Function 1)
Pin Peripheral
SWCLK –
SWD –
– –
– –
Bit name Initial
0x00
DBRUN 0
0x0
0x0
0x0
0x00
– 0
P6INT 0
P5INT 0
P4INT 0
P3INT 0
P2INT 0
P1INT 0
P0INT 0
Seiko Epson Corporation
Reset R/W
– R –
H0 R/W –
H0 R/W
H0 R/W
H0 R/W
– R –
H0 R/W –
H0 R/W
H0 R/W
H0 R/W
– R –
– R
–
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W –
H0 R/W –
H0 R/W
H0 R/W
H0 R/W
PDSELy = 1
PDyMUX = 0x2
(Function 2)
Pin Peripheral Pin
– – –
– – –
– CLG OSC4
– CLG OSC3
Reset R/W
– R –
R/WP –
H0
H0 R/WP
– R –
H0 R/WP –
– R –
– R
–
H0 R
H0 R
H0 R
H0 R
H0 R
H0 R
H0 R
32 48
Remarks
pin pin
– –
✓ ✓
✓ ✓
✓ ✓
✓ ✓
– –
✓ ✓
✓ ✓
✓ ✓
✓ ✓
– –
– –
✓ ✓
✓ ✓
✓ ✓
✓ ✓
– –
✓ ✓
✓ ✓
✓ ✓
✓ ✓
32 48
PDyMUX = 0x3
pin pin
(Function 3)
Peripheral Pin
– –
✓ ✓
– –
✓ ✓
– –
✓ ✓
– –
✓ ✓
32 48
Remarks
pin pin
– –
✓ ✓
✓ ✓
– –
✓ ✓
– –
– –
✓ ✓
✓ ✓
✓ ✓
✓ ✓
✓ ✓
✓ ✓
–
✓
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
64
pin
–
✓
✓
✓
✓
–
✓
✓
✓
✓
–
–
✓
✓
✓
✓
–
✓
✓
✓
✓
64
pin
✓
✓
✓
✓
64
pin
–
✓
✓
–
✓
–
–
✓
✓
✓
✓
✓
✓
✓