Table of Contents
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CONTENTS
Preface ......................................................................................................................................i
Notational conventions and symbols in this manual ................................................................i
1 Overview ........................................................................................................................1-1
1.1 Features .......................................................................................................................... 1-1
1.2 Block Diagram ................................................................................................................. 1-4
1.3 Pins ................................................................................................................................. 1-5
1.3.1 Pin Configuration Diagram................................................................................ 1-5
1.3.2 Pin Descriptions ................................................................................................ 1-8
2 Power Supply, Reset, and Clocks ...............................................................................2-1
2.1 Power Generator (PWGA) ............................................................................................... 2-1
2.1.1 Overview ........................................................................................................... 2-1
2.1.2 Pins ................................................................................................................... 2-1
2.2 System Reset Controller (SRC) ....................................................................................... 2-3
2.2.1 Overview ........................................................................................................... 2-3
2.2.2 Input Pin ............................................................................................................ 2-4
2.2.3 Reset Sources .................................................................................................. 2-4
2.2.4 Initialization Conditions (Reset Groups) ............................................................ 2-5
2.3 Clock Generator (CLG) .................................................................................................... 2-5
2.3.1 Overview ........................................................................................................... 2-5
2.3.2 Input/Output Pins ............................................................................................. 2-6
2.3.3 Clock Sources .................................................................................................. 2-6
2.3.4 Operations ........................................................................................................ 2-9
2.4 Operating Mode ............................................................................................................. 2-14
2.4.1 Initial Boot Sequence ....................................................................................... 2-14
2.4.2 Transition between Operating Modes .............................................................. 2-14
2.5 Interrupts ........................................................................................................................ 2-16
2.6 Control Registers ........................................................................................................... 2-16
PWGA Control Register ...................................................................................................... 2-16
CLG System Clock Control Register .................................................................................. 2-17
CLG Oscillation Control Register ........................................................................................ 2-18
CLG IOSC Control Register ................................................................................................ 2-19
CLG OSC1 Control Register ............................................................................................... 2-19
CLG OSC3 Control Register ............................................................................................... 2-20
CLG Interrupt Flag Register ................................................................................................ 2-22
CLG Interrupt Enable Register............................................................................................ 2-22
CLG FOUT Control Register ............................................................................................... 2-23
CLG Oscillation Frequency Trimming Register 1 ................................................................ 2-24
CLG Oscillation Frequency Trimming Register 2 ................................................................ 2-24
CLG Oscillation Frequency Trimming Register 3 ................................................................ 2-25
3 CPU and Debugger ......................................................................................................3-1
3.1 Overview ......................................................................................................................... 3-1
3.2 CPU ................................................................................................................................. 3-1
3.3 Debugger ........................................................................................................................ 3-1
3.3.1 List of Debugger Input/Output Pins .................................................................. 3-1
3.3.2 External Connection ......................................................................................... 3-1
3.4 Reference Documents .................................................................................................... 3-2
ii
- Contents -
Regulator Operation Mode ......................................................................... 2-2
Regulator Voltage Mode ............................................................................. 2-2
Seiko Epson Corporation
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
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